[video member=pervognsen stream_platform=twitch project=bitwise title="Logic Design, Part 5" vod_platform=youtube id=njaGzTDGZTE annotator=Miblo]
[0:06][Recap and set the stage for the day continuing with the simulator][:emulation :speech]
[2:30][Check out the graph of Example7, our adder][:"debug visualisation" :"logic design" :run]
[3:32][Simulate our adder][:emulation :"logic design"]
[5:16][Verify our adder simulation using python's own addition functionality][:emulation :"logic design"]
[6:41][:Run it and fail to hit our verification assertion, with a few words on this brute-force verification][:emulation :"logic design"]
[8:33][Simulate our subtraction circuit][:emulation :"logic design" :run]
[9:14][:Run it to find that our subtraction works too][:emulation :"logic design"]
[9:36][Simulate our less-than comparison circuit][:emulation :"logic design" :run]
[10:37][:Run it to find that our less-than comparison does not work][:emulation :"logic design"]
[15:06][@rygorous][carry = below, (i.e. unsigned less than). Definitely not <=. Argh, no, I'm thinking x86. x86 CMP is a SUB which sets the carry flag to "borrow", which is !carry, i.e. you need to invert. Your carry is unsigned >=, as in, regular (non-inverted) carry is]
[15:10][Negate the result of the less-than comparison in Example10][:"logic design"]
[15:58][:Run it to find that our inverted less-than comparison succeeds][:emulation :"logic design"]
[16:19][Respecify Example10 as greater-than-or-equal-to, and simulate its signed comparison][:emulation :"logic design"]
[18:29][:Run it to find that our signed greater-than-or-equal-to comparison fails][:emulation :"logic design"]
[20:29][Enable join() to interpret NOT as an unsigned operation][:"logic design"]
[21:35][Change our geus simulation test to assert that x < y (i.e. less-than), and find that it passes][:emulation :"logic design" :run]
[21:53][Understanding the lts comparison and bitwise negation before sign-extension of the second operand][:"logic design" :speech]
[24:08][Set up to cover fast adders][:"logic design" :speech]
[25:31][Understanding ripple-carry adder :performance, with a mention of FO4][:"logic design" :speech]
[28:40][Speculative execution, and carry-select addition][:"logic design" :speech]
[31:15][Set up to easily instantiate different sized adders][:"logic design"]
[33:34][Define Example11 as a divide-and-conquer ripple-carry adder][:"logic design"]
[37:08][Simulate Example11 to see that it works][:emulation :"logic design" :run]
[37:31][Define Example12 using speculative execution on Example11 to form a carry-select adder][:"logic design"]
[38:48][Simulate Example12 to see that it works][:emulation :"logic design" :run]
[39:21][Understanding why the carry-select adder is faster than ripple-carry][:"logic design" :performance :speech]
[42:16][Introduce conditional_sum_adder()][:"logic design"]
[42:45][@cubercaleb][data.medicare.gov.json?]
[42:52][Implement conditional_sum_adder()][:"logic design"]
[45:41][Check out the graph of Example12, the carry-select adder][:"debug visualisation" :"logic design" :run]
[46:26][Define Example13 as a conditional-sum adder][:"logic design"]
[48:25][Check out the graph of Example13, the conditional-sum adder][:"debug visualisation" :"logic design" :run]
[49:02][Instantiate a 16-bit conditional-sum adder, and check out its graph][:"debug visualisation" :"logic design" :run]
[50:28][Simulate our conditional-sum adder][:emulation :"logic design"]
[51:46][:Run it to find that the conditional-sum adder does not work][:emulation :"logic design"]
[54:14][Investigate the possibility that the simulator is not correctly masking][:"code generation" :emulation :"logic design"]
[1:04:45][Step through compile() to see how it treats our operands, and find that the operands don't have the same length][:"code generation" :emulation :"logic design" :run]
[1:09:14][Consult the graph of the conditional-sum adder to see a node erroneously containing bit\[5\]][:"debug visualisation" :"logic design" :run]
[1:09:39][Make Example13, the conditional-sum adder, only output the lower bits][:emulation :"logic design"]
[1:10:47][:Run it to see that we pass the test][:emulation :"logic design"]
[1:11:06][Set up to cover carry lookahead adders][:"logic design" :speech]
[1:11:33][Speculative execution in carry lookahead adders][:"logic design" :speech]
[1:13:45][Restructuring a ripple-carry adder with indexable bits, towards a carry lookahead adder][:"logic design" :speech]
[1:19:38][Parallelising the carry circuit][:"logic design" :optimisation :speech]
[1:29:37][Introduce carry_lookahead_adder() and linear_scan()][:"logic design"]
[1:33:49][Define Example14 as a linear_scan() of XOR][:"logic design"]
[1:34:56][Check out the graph of the XOR linear_scan][:"debug visualisation" :"logic design" :run]
[1:35:51][Define Example15 as a carry lookahead adder][:"logic design"]
[1:36:28][Check out the graph of the carry lookahead adder][:"debug visualisation" :"logic design" :run]
[1:36:51][Simulate the carry lookahead adder][:emulation :"logic design"]
[1:37:29][:Run the carry lookahead adder simulation to find that it doesn't work][:emulation :"logic design"]
[1:38:59][Fix pg_compose() to return the operands in the correct order][:"logic design"]
[1:40:36][Consult the carry lookahead adder graph to determine that it is off-by-one][:"debug visualisation" :"logic design" :run]
[1:41:56][Make carry_lookahead_adder() shift the carry right one bit][:"logic design"]
[1:44:29][@rygorous][I think you meant c\[1:\] \@ 0][:"logic design"]
[1:44:35][Fix carry_lookahead_adder() to slice the carry the correct way][:"logic design"]
[1:44:42][:Run the carry lookahead adder simulation to find that it passes][:emulation :"logic design"]
[1:45:24][Check out the graph of the correct carry lookahead adder][:"debug visualisation" :"logic design" :run]
[1:46:15][Introduce bruteforce_logarithmic_scan()][:"logic design"]
[1:47:49][Test our bruteforce_logarithmic_scan() and check out the graph][:"debug visualisation" :"logic design" :run]
[1:48:06][Wrap the pg_compose into a PG module][:"logic design"]
[1:49:38][Check out the graph of our carry lookahead adder with bruteforce logarithmic scan and PG module][:"debug visualisation" :"logic design" :run]
[1:50:08][Instantiate an 8-bit carry lookahead adder and check out its graph][:"debug visualisation" :"logic design" :run]
[1:51:22][Introduce sklansky_scan()][:"logic design"]
[1:54:42][Instantiate a 4-bit carry lookahead adder with sklansky_scan and check out its graph][:"debug visualisation" :"logic design" :run]
[1:55:33][Compare bruteforce and Sklansky scan 8-bit carry lookahead adder graphs][:"debug visualisation" :"logic design" :run]
[1:56:37][@spriithy][What does the \@ operator do?][:language]
[1:57:09][Introduce brent_kung_scan() and rename unzip() to interleave()][:"logic design"]
[2:04:50][Instantiate a 4-bit carry lookahead adder with Brent Kung scan, and check out its graph][:"debug visualisation" :"logic design" :run]
[2:08:41][That's it for fast adders][:"logic design" :speech]
[2:10:16][Recommend Guy Even's 'On teaching fast adder designs: revisiting Ladner & Fischer'[ref
    author="Guy Even"
    title="On teaching fast adder designs: revisiting Ladner & Fischer"
    url=http://www.eng.tau.ac.il/~guy/Papers/PPC_adder_tutorial.pdf]][:"logic design" :research]
[2:11:16][That's it for today][:speech]
[/video]
