[video member=miotatsu stream_platform=twitch project=riscy title="Studying the Machine Interrupt Registers" vod_platform=youtube id=ug5WkCROkOk annotator=Miblo]
[0:06][Recap and set the stage for the day]
[0:51][Intuition on two's complement][:blackboard]
[4:10][We are counting with zeroes][:blackboard]
[9:03][Revisit instructions.scala[ref
    site=GitHub
    page=instructions.scala
    url=https://github.com/ucb-bar/rocket/blob/master/src/main/scala/instructions.scala]
    and :research register-transfer level[ref
    site=Wikipedia
    page="Register-transfer level"
    url=https://en.wikipedia.org/wiki/Register-transfer_level]]
[15:55][Come to understand how to specify that rs1 represents an immediate or a register, thanks to the reply to the "Confusion Regarding Freedom E SDK inline asm" forum thread[ref
    site="SiFive Forums"
    page="Confusion Regarding Freedom E SDK inline asm"
    url=https://forums.sifive.com/t/confusion-regarding-freedom-e-sdk-inline-asm/383]][:blackboard]
[18:25][Read clear_csr() to put csrrc into perspective with our new understanding of pseudo-instructions and the i vs r hints][:asm :blackboard :research]
[22:24][Read about CSRRCI in the CSR Instructions section of the User-Level ISA Specification[ref
    site="RISC-V"
    page="User-Level ISA Specification v2.1"
    url=https://riscv.org/specifications]][:research]
[23:05][Walk through clear_csr() again][:asm :research]
[28:53][GNU Assembly Syntax: Constraints and Syntax[ref
    site=ericw.
    page="A Tiny Guide to GCC Inline Assembly"
    url=http://ericw.ca/notes/a-tiny-guide-to-gcc-inline-assembly.html]][:asm :blackboard :research]
[35:15][Continue reading clear_csr()][:asm :research]
[40:21][Pop back up to the top of the stack, to reset_demo(), and read about the currently allocated RISC-V machine-level CSR addresses[ref
    site="RISC-V"
    page="Draft Privileged ISA Specification v1.9.1"
    url=https://riscv.org/specifications/privileged-isa/]][:research]
[44:11][Read about Machine Interrupt Registers, including the mie (machine interrupt-enable) register][:hardware :research]
[49:26][Note how common it is in plic_driver.c for us to compute an address of a memory mapped register in order to mess with interrupts][:research]
[51:45][A few words on the sponge mode that we're in]
[52:50][Continue reading about the Machine Interrupt Registers][:research]
[58:33][Return to demo_gpio.c and come to understand the clear_csr() calls in relation to the documentation][:research]
[1:06:48][We're out of time for today]
[/video]
