[video member=pervognsen stream_platform=twitch project=bitwise title="Logic Design" vod_platform=youtube id=CQ-LQTEWLdc annotator=Miblo]
[0:00][Recap and set the stage for the day on :"logic design"][:speech]
[2:10][Introducing :"logic design", gates and operation cost][:speech]
[7:39][Set up to design and visualise a simple circuit fragment][:"logic design" :speech]
[8:42][Define Example1 module as a simple NOT circuit][:"logic design"]
[10:40][:Run our Graphviz generator and checkout the graph for Example1][:"debug visualisation" :"logic design"]
[11:16][Add another NOT node to Example1][:"logic design"]
[11:37][:Run it to see our additional NOT node][:"debug visualisation" :"logic design"]
[11:42][Building up circuits of primitives][:"logic design" :speech]
[12:43][Define Not module to show the possibility to replace builtin primitives][:"logic design"]
[15:20][:Run it to see our graphed handwritten Not node][:"debug visualisation" :"logic design"]
[17:45][Change Example1 to contain two input nodes][:"logic design"]
[18:53][:Run it to see our circuit with two inputs][:"debug visualisation" :"logic design"]
[18:58][Add two custom Not nodes to Example1][:"logic design"]
[19:31][:Run it to see our custom Not nodes][:"debug visualisation" :"logic design"]
[19:48][Typical module hierarchy][:"logic design" :speech]
[20:21][Define Xor module for Not to use][:"logic design"]
[22:02][:Run the Graphviz generator on all levels of our module hierarchy][:"debug visualisation" :"logic design"]
[23:04][Set up to demonstrate universality through generation of the circuit corresponding to a Python boolean function / table][:"logic design" :speech]
[25:03][Produce the formula for XOR from its truth table using the sum of products representation][:"logic design" :speech]
[29:29][Set up to create a general truth table-to-circuit converter][:"logic design" :speech]
[31:56][Introduce table_to_circuit(), reduce_or() and reduce_and()][:"logic design"]
[38:23][Test reduce_or()][:"logic design"]
[38:50][:Run it to see that it does what you hope it does][:"debug visualisation" :"logic design"]
[39:00][Add a third input to our reduce_or() call in Example2][:"logic design"]
[39:09][:Run it to see that it's incorrect][:"debug visualisation" :"logic design"]
[39:29][Fix typo in our reduce_or() call][:"logic design"]
[39:39][:Run it to see our cascaded reduction of inputs][:"debug visualisation" :"logic design"]
[40:21][Test table_to_circuit()][:"logic design"]
[41:02][:Run it to see our Xor circuit][:"debug visualisation" :"logic design"]
[41:26][Sum of products][:"logic design" :speech]
[42:05][Introduce tabulate() to turn a boolean function into its corresponding truth table][:"logic design"]
[48:26][Introduce function_to_circuit()][:"logic design"]
[50:30][Test function_to_circuit()][:"logic design"]
[51:04][:Run it to see that it produces the minimal representation for an AND gate, but not an OR gate][:"debug visualisation" :"logic design"]
[51:57][Illustrate the wasteful (yet correct) nature of this OR circuit][:"logic design" :speech]
[54:05][Set up to illustrate the inability of sum of products to scale][:"logic design" :speech]
[55:41][Produce a three-input XOR circuit][:"logic design"]
[56:45][:Run it to see our greater number of terms][:"debug visualisation" :"logic design"]
[57:02][Add a fourth input to our XOR circuit][:"logic design"]
[57:18][:Run it to see our exponentially growing graph, noting that this is bound to happen with a two-level circuit][:"debug visualisation" :"logic design"]
[58:52][Summarise our establishment of universality][:"logic design" :speech]
[59:50][Q&A][:speech]
[1:00:30][Note the assumption that viewers are comfortable with programming][:speech]
[1:02:02][Set up to cover multiplexers and Shannon expansion][:"logic design" :speech]
[1:02:55][Define Example3 as a multiplexer using the "when" node][:"logic design"]
[1:05:24][:Run it to see our "when" node][:"debug visualisation" :"logic design"]
[1:06:33][Define a custom When node][:"logic design"]
[1:08:07][:Run it to see our custom sum-of-products When node][:"debug visualisation" :"logic design"]
[1:08:31][Hand write a more efficient When node][:"logic design"]
[1:09:06][:Run it to see this more efficient representation][:"debug visualisation" :"logic design"]
[1:10:54][Shannon expansion[ref
    site=Wikipedia
    page="Boole's expansion theorem"
    url=https://en.wikipedia.org/wiki/Boole%27s_expansion_theorem]][:"logic design" :speech]
[1:16:19][Introduce function_to_muxes() and expand()][:"logic design"]
[1:21:04][Test function_to_muxes()][:"logic design"]
[1:22:33][:Run it to see our Shannon expanded AND circuit][:"debug visualisation" :"logic design"]
[1:25:02][Test function_to_muxes() on a multi-input XOR][:"logic design"]
[1:26:29][:Run it to see our neat XOR circuit thanks to the implicit BDDs (binary decision diagrams) in our memoization][:"debug visualisation" :"logic design"]
[1:27:17][Temporarily disable memoization][:"logic design"]
[1:27:39][:Run it to see our full exponential circuit, and consider its potential for memoization][:"debug visualisation" :"logic design"]
[1:29:04][:Run it with our re-enabled memoization and consider the ready compaction of multiplexers thanks to binary decision diagrams[ref
    site=Wikipedia
    page="Binary decision diagram"
    url=https://en.wikipedia.org/wiki/Binary_decision_diagram]][:"debug visualisation" :"logic design"]
[1:30:28][Add a fifth input to our function_to_muxes() test][:"logic design"]
[1:30:47][:Run it to see our compact circuit, and consider our ability to formally compare reduced BDDs of functions][:"debug visualisation" :"logic design"]
[1:33:00][Summarise the stream][:"logic design" :speech]
[1:34:55][Q&A][:speech]
[1:35:06][@xanatos387][Are six input bits often utilized? It seems like most things would be like <=3 inputs, or eight or more inputs (bytes and beyond). Six just seems like an odd number, not even a power of 2!][:"logic design"]
[1:38:13][@quovadit][Plans to implement circuit optimization algorithms?][:"logic design" :optimisation]
[1:39:31][That's it][:speech]
[/video]
