[video member=miotatsu stream_platform=twitch project=riscy title="Understanding the Relationship Between the PLIC, mie, and mstatus MIE Bit" vod_platform=youtube id=9ZiHmPhOrQ4 annotator=Miblo]
[0:18][Mention John Gustafson's talk on a new way of encoding decimal numbers[ref
    site=insideHPC
    page="John Gustafson presents: Beyond Floating Point – Next Generation Computer Arithmetic"
    url=http://insidehpc.com/2017/02/john-gustafson-presents-beyond-floating-point-next-generation-computer-arithmetic/]]
[3:16][Set the stage for the day]
[4:33][Read about mstatus[ref
    site="RISC-V"
    page="Draft Privileged ISA Specification v1.9.1"
    url=https://riscv.org/specifications/privileged-isa/]][:hardware :research]
[5:24][@miblo][Haha! I noticed myself doing that and wanted to break the same habit! (Without success, I think)]
[6:09][:Research the Machine Status Register][:hardware]
[8:32][Consult demo_gpio.c and plic_driver.c and wonder what the machine-external and machine-timer interrupts bits are doing][:hardware :research]
[12:08][Wonder also why we have a separate Coreplex-Local Interrupts controller][:hardware]
[14:35][Continue reading about the machine-mode status register (mstatus)][:hardware :research]
[20:27][Summarise how the mie bit in the mstatus register is being used][:hardware :research]
[21:36][Read about privilege levels][:hardware :research]
[24:32][Determine that the PLIC only handles global interrupts, and read about local interrupt sources][:hardware :research]
[28:01][Read about Interrupt Targets and Hart Contexts][:hardware :research]
[29:19][Consult the PLIC diagram][:blackboard :hardware :research]
[31:00][Continue reading about the interrupts in terms of the mip][:hardware :research]
[39:47][Note that PLIC_enable_interrupt() and PLIC_disable_interrupt() happen on a per-thread basis][:hardware :research :threading]
[41:58][Review the documentation on Machine Interrupt Registers (mip and mie)][:hardware :research]
[46:53][Consult the table on mstatus and consider the difference between mip and mie][:hardware :research]
[49:01][Return to demo_gpio.c, note that the clear_csr() calls in reset_demo() are not disabling software interrupts, and consider asking why][:research]
[53:44][Skim over demo_gpio.c in general][:research]
[55:15][@tenbroya][Heyo]
[55:57][@tenbroya][(it's James from the HMN IRC)]
[56:04][Continue skimming over demo_gpio.c][:research]
[58:35][RISC-V Assembly Programmer's Handbook[ref
    site=RISC-V
    page="User-Level ISA Specification v2.1"
    url=https://riscv.org/specifications]]
[59:28][Read about the Coreplex-Local Interrupts (CLINT)[ref
    site="SiFive Developers"
    page="E3 Coreplex Manual"
    url=https://static.dev.sifive.com/pdfjs/web/viewer.html?file=https://static.dev.sifive.com/SiFive-E3-Coreplex-v1.2.pdf]][:hardware :research]
[1:02:44][Read about MSIP Registers][:hardware :research]
[1:03:40][That's all the time we have for today]
[/video]
