[video member=miotatsu stream_platform=twitch project=riscy title="Understanding PLIC_Init & PLIC_set_threshold" vod_platform=youtube id=uPnUOi4DYIA annotator=Miblo]
[0:23][Recap and set the stage for the day][:blackboard :hardware]
[1:37][Determine to understand the PLIC_ENABLE_OFFSET enables][:hardware]
[3:52][:Research the Platform-Level Interrupt Controller, :Memory Map[ref
    site="SiFive Developers"
    page="E3 Coreplex Manual"
    url=https://static.dev.sifive.com/pdfjs/web/viewer.html?file=https://static.dev.sifive.com/SiFive-E3-Coreplex-v1.2.pdf]][:hardware]
[6:35][:Research Target Interrupt Enables][:hardware]
[7:57][demo_gpio.c number_sources passing to PLIC_init()][:hardware]
[11:55][Consult the Freedom E310-G000 Manual[ref
    site="SiFive Developers"
    page="Freedom E310-G000 Manual"
    url=https://www.sifive.com/documentation/chips/freedom-e310-g000-manual/] to see why PLIC_NUM_INTERRUPTS is 52][:hardware]
[15:23][Investigate why we are clearing (num_sources + 8) / 8 bytes][:hardware :research]
[19:36][@insofaras][Is there 1 bit per interrupt?]
[19:43][@miblo][Does the 3-bitness of the interrupts matter, perhaps?]
[20:19][@insofaras][The + 8 / 8 seems suspiciously like a round-up to me]
[21:28][Investigate why we are shifting up the hart_id by PLIC_ENABLE_SHIFT_PER_TARGET][:research]
[22:10][@insofaras][Yeah, it would pass 7. I mean like if you passed in a count that isn't a multiple of 8, it makes sure you clear the byte required for the left over bits]
[27:33][Bit shifting up by 7, and binary values in hexadecimal][:blackboard]
[31:37][@insofaras][I think all the interrupt enable bits are packed together in the first target, so it just needs to set 7 bytes to 0 to clear them all]
[32:41][@insofaras][I'm going by the text in the Coreplex manual[ref
    site="SiFive Developers"
    page="u5 Coreplex Manual"
    url=https://dev.sifive.com/documentation/u5-coreplex-series-manual/] section 6.4, and 6.5 which says the interrupt enables use the same format as in 6.4]
[35:25][:Research the Interrupt Pending Bits and Target Interrupt Enables in the Freedom Everywhere's Coreplex manual][:hardware]
[38:47][@insofaras][Yeah with 52 interrupts, in a packed bit array, that's 52 bits, or 7 bytes]
[39:23][Come to fully understand why we are shifting up the hart_id by PLIC_ENABLE_SHIFT_PER_TARGET][:research :blackboard]
[43:22][What the hart_id shifting accomplishes][:blackboard]
[45:11][@miblo][Did we establish what "hart" stands for?]
[45:34][@insofaras][Oh, wait, in the Terminology section it says: HARdware Thread]
[46:19][Consult the Terminology section in the Coreplex manual][:research]
[49:26][@popcorn0x90][HiFive1 doesn't look that big]
[50:01][Note HARdware Thread and the computation of the interrupt size clearing][:blackboard :hardware]
[53:36][Come to understand how the setting of all priorities to 0 is being accomplished][:research :hardware]
[57:54][Come to understand how the setting of the threshold to 0 is being accomplished][:research :hardware]
[1:04:34][Swiftly read PLIC_set_threshold(), before moving on to PLIC_enable_interrupt()][:research :hardware]
[1:05:47][Determine to take a closer look at PLIC_enable_interrupt()]
[/video]
