[video member=miotatsu stream_platform=twitch project=riscy title="Getting Back to the Code" vod_platform=youtube id=ozKRGzd6Q4E annotator=Miblo]
[0:08][Recap and set the stage for the day]
[0:57][Sign extension in two's complement[ref
    site=Wikipedia
    page="Sign extension"
    url=https://en.wikipedia.org/wiki/Sign_extension]][:blackboard :research]
[7:45][@hossein1387][You can do a two's complement on 1000_0000 to get the positive value]
[10:07][:Research setting only the most significant bit in two's complement[ref
    site=Wikipedia
    page="Two's complement"
    url=https://en.wikipedia.org/wiki/Two's_complement]]
[15:19][Refresh our memory on the Base Instruction Formats and the Immediates with regard to sign extension[ref
    site=RISC-V"
    page="User-Level ISA Specification v2.1"
    url=https://riscv.org/specifications]][:research]
[19:25][Read about the Integer Register-Immediate Instructions][:research]
[22:54][Adding unsigned immediates][:blackboard]
[23:25][@hossein1387][For the adder it does not matter if it's a sign or signed]
[26:48][Adding unsigned 42 to 128 using sign extension (with incorrect results)][:blackboard]
[31:47][@hossein1387][But I remember in Computer Architecture class, for ALU, depending on the instruction being signed or unsigned, we had to do a two's complement before passing the number to the, let's say, adder]
[34:27][@hossein1387][I have a list of instructions for RISC-V and I can only see ADD and ADDI]
[35:28][Consider unsigned immediate adding to be a gotcha if coding in assembly][:asm :blackboard :research]
[38:08][@hossein1387][Sorry, I found two more. This what I found: ADDI ADD ADDIW ADDW]
[40:27][@hossein1387][By the way I am reading the RTL for instructions]
[41:25][@hossein1387][[ref
    site=GitHub
    page=instructions.scala
    url=https://github.com/ucb-bar/rocket/blob/master/src/main/scala/instructions.scala]]
[44:53][Read about the Control and Status Register Instructions with a view to understanding the < 32 test in clear_csr()][:research]
[50:29][Read about the rs1 and rd, and RISC-V user-level base integer register state][:research]
[54:48][Read about the types of immediate produced by RISC-V instructions][:research]
[1:01:09][Determine to ask in the SiFive Forums about the < 32 test in clear_csr()]
[/video]
