[video member=miotatsu stream_platform=twitch project=riscy title="Understanding read_csr(mhartid)" vod_platform=youtube id=C0A-EQuQP0U annotator=Miblo]
[0:06][Set the stage for the day]
[0:42][Read through plic.h]
[2:21][Read through encoding.h, where we find read_csr()]
[6:33][Read freedom-e300-hifive1/platform.h]
[8:07][Consult the manual: Memory Map, and Interrupts[ref
    site="SiFive Developers"
    page="Freedom E310-G000 Manual"
    url=https://www.sifive.com/documentation/chips/freedom-e310-g000-manual/]][:research]
[11:59][Continue reading plic_driver.c with a view to understanding read_csr(mhartid)]
[13:17][Consult the User-Level spec on CSR instructions[ref
    site="RISC-V"
    page="User-Level ISA Specification v2.1"
    url=https://riscv.org/specifications/]][:asm :research]
[19:05][Atomic Read and Set Bits in CSR][:blackboard :asm]
[26:50][Consult the Privileged ISA Spec on CSR [ref
    site="RISC-V"
    page="Draft Privileged ISA Specification v1.9.1"
    url=https://riscv.org/specifications/privileged-isa/]][:asm :research]
[30:30][Begin to understand the csrr instruction, aided by the table of CSR addresses][:research :asm]
[34:34][Learn that mhartid is the "Hardware thread ID"][:research :asm]
[39:56][Read about the Machine-Level ISA[ref
    site="RISC-V"
    page="Draft Privileged ISA Specification v1.9.1"
    url=https://riscv.org/specifications/]][:asm :hardware :research]
[45:25][@insofaras][I think the %0 refers to the _tmp variable]
[45:59][@insofaras][The GCC inline :asm syntax is pretty weird]
[46:56][Summarise what read_csr(mhartid) is doing]
[47:33][Move on to the next line of code]
[50:20][The parameters that csrr takes, and what read_csr() and mhartid are][:blackboard]
[53:47][Discover what _AC() and PLIC_ENABLE_OFFSET() are]
[56:51][Determine to consult the spec tomorrow]
[/video]
