[video member=pervognsen stream_platform=twitch project=bitwise medium=research title="RISC-V Toolchain" vod_platform=youtube id=g6UJGcrQNY8 annotator=Miblo]
[0:08][Recap and set the stage for the day][:speech]
[1:32][Demo the new command line interface, with and without the -lazy flag][:run :ui]
[3:05][Review the new support for different backend targets]
[6:23][A few words on appropriately deferring work][:speech]
[7:52][Continued review of the multiple backend target support]
[10:06][Review the new support of conditional compilation of source files based on target]
[14:47][Review the libc binding contributions from @twicetimes]
[17:17][Review the new Ion bindings of a subset of SDL, and full port of Noir to Ion][:language :library]
[22:02][Review Ion's destination-oriented varargs[ref
    site=cppreference.com
    page=va_start
    url=http://en.cppreference.com/w/c/variadic/va_start]][:language]
[29:30][Step in to test_va_list() to demo Ion's varargs][:language :run]
[30:44][Explain the implementation of Ion's varargs][:language]
[34:28][Q&A][:speech]
[35:00][@nothings2][If you have "foo.ion" and "foo_linux.ion" does it compile both on linux, or only the most specific?][:"file io"]
[36:46][@nothings2][@pervognsen We found it useful in cdep to have the ability to have a common file (e.g. for all POSIX systems) and then override only for some platforms, but I don't think you have that ability with your exclude system, which will use all files that match so you can't have a fallback?]
[38:48][Demo Ion's ability to temporarily exclude files][:language :run]
[40:47][@cmdrkroz][@pervognsen What about static constant booleans that cause conditional compilation (a la java, which doesn't compile bytecode for conditionals that are always false)][:language]
[43:21][Set up to start work on RISC-V stuff,[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf] adding a "riscv" project to Visual Studio][:admin :isa]
[56:28][2.2 Base Instruction Formats[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf] of RISC-V vs x86][:isa]
[1:07:31][Why are the function bits split across multiple positions?[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]]
[1:08:37][@xanatos387][Seems like its just to keep the rd / rs1 / rs2 always in the same spots?][:isa]
[1:08:48][@nothings2][@pervognsen I have no idea, I can't see any downside to swapping funct3 and rd][:isa]
[1:09:35][Different immediate fields in RISC-V's core instruction formats[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[1:14:22][@rygorous][It's usually "sign extend and then do something else" or "do something else then sign extend", so the sign extend is on the critical path][:isa]
[1:14:30][@nothings2][It probably does get sign extended in 64-bit?][:isa]
[1:15:12][2.3 Immediate Encoding Variants[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[1:18:06][2.4 Integer Computational Instructions[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf] with a look at arithmetic right-shift of negative values in C[ref
    author=ANSI
    title="ISO/IEC 9899: Information technology – Programming languages – C"
    url=http://www.open-std.org/jtc1/sc22/wg14/www/docs/n1256.pdf]][:isa :language]
[1:24:24][Demo the strange behaviour of arithmetic right-shift of -1][:language :run]
[1:26:21][2.4 Integer Computational Instructions, continued[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[1:28:23][LUI (load upper immediate)[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf], with a specific example of its use in conjunction with an addi][:isa]
[1:34:29][@rygorous][The lo / hi stuff needs to account for the signedness of lo][:isa]
[1:34:46][@rygorous][i.e. if the %lo bits end up with the top bit (sign) set, you need to increment %hi by 1][:isa]
[1:35:00][Continued example of LUI, and AUIPC (add upper immediate to pc)[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[1:38:25][Integer Register-Register Operations, and 2.5 Control Transfer Instructions[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[1:43:53]["jump and link" in RISC-V[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf] vs "call and return" in x86][:isa :optimisation]
[1:47:56][Conditional Branches[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf], with a comparison with cmp then jle in x86][:asm :isa]
[1:53:41][2.6 Load and Store Instructions[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[2:03:18][Load / Store instruction addressing modes in ARM, vs RISC-V's single "mode"[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[2:05:19][FENCE.I with an allusion to the Privileged spec,[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 2: Privileged Architecture"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.10.pdf] and 2.8 Control and Status Register Instructions[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[2:10:39][Wind it down with the determination to look further into the LUI and sign-extension stuff][:speech]
[2:11:23][Q&A][:speech]
[2:12:06][@elventhief][What's your coding approach going to start as?]
[2:14:19][@miotatsu][@pervognsen You do just do lui followed by addi. I didn't know about the fix-up stuff [@rygorous Fabien] mentioned but I am looking at binutils source right now and it looks like it %hi is doing the fix-up like what @rygorous suggested earlier]
[2:15:06][That's it][:speech]
[/video]
