[video member=pervognsen stream_platform=twitch project=bitwise title="Sequential Logic" vod_platform=youtube id=2XKxrkZC1GI annotator=Miblo]
[0:07][Recap and set the stage for the day moving on to :"sequential logic"][:"logic design" :speech]
[0:30][Review the off-stream bug-fix and :optimisation to nonrestoring_binary_divider()][:"logic design" :research]
[3:59][Briefly note real-number approaches to division, including Newton's method,[ref
    site=Wikipedia
    page="Newton's method"
    url=https://en.wikipedia.org/wiki/Newton%27s_method] Goldschmidt[ref
        site=Wikipedia
        page="Division algorithm / Goldschmidt division"
        url=https://en.wikipedia.org/wiki/Division_algorithm#Goldschmidt_division] and SRT division[ref
            site=Wikipedia
            page="Division algorithm / SRT division"
            url=https://en.wikipedia.org/wiki/Division_algorithm#SRT_division]][:"logic design" :speech]
[8:15][Moving on from deterministic parallel functional programming to sequencing stateful systems][:"logic design" :"sequential logic" :speech]
[11:15][Stateful systems][:"sequential logic" :speech]
[12:57][The basic stateful component:  register / flip-flop][:"sequential logic" :speech]
[16:31][Understanding our existing RegisterNode][:"sequential logic" :research]
[19:02][Comment out the SerialMultiplier module and remove "enable" from the RegisterNode][:"sequential logic"]
[20:02][Check out the code for Example37 in the context of our move to a stateful system][:"sequential logic" :research]
[22:08][Spec out a Counter class][:"sequential logic" :speech]
[29:31][Spec out simulation of the system every time][:emulation :"sequential logic" :speech]
[31:23][Understanding the necessity of double-buffering][:"sequential logic" :speech]
[33:32][Set up to implement our stateful system][:"sequential logic" :speech]
[34:50][Begin to implement RegisterNode privately setting and type-checking the "next" property][:"sequential logic"]
[37:11][:Run it to see that the RegisterNode type-checking works][:"sequential logic"]
[37:20][Enable set_next() in RegisterNode to convert literals to their expected type[ref
    site="Tutorials, Python Courses: Online and On Site"
    page="Properties vs. Getters and Setters"
    url=https://www.python-course.eu/python3_properties.php]][:"sequential logic"]
[38:20][:Run it to see that the type-conversion works][:"sequential logic"]
[38:56][Define Example38 as a counter][:"sequential logic"]
[42:02][Check out the graph of our counter][:"debug visualisation" :"sequential logic" :run]
[42:39][Introduce make_register() in our Linearizer for its RegisterNode() to use][:emulation :"sequential logic"]
[49:09][Test linearizing Example38 to see that the inliner doesn't cannot handle our RegisterNode][:emulation :"sequential logic" :run]
[49:35][Introduce RegisterNode() in our Transformer][:emulation :"sequential logic"]
[50:51][Check out our linearized Example38][:emulation :"sequential logic" :run]
[52:12][Change RegisterNode() in the Transformer to set the name and increment the counter inline][:emulation :"sequential logic"]
[54:20][Check out our linearized Example38 to see t2 computed earlier][:emulation :"sequential logic" :run]
[54:52][Enable linearizer() to return the registers to set the next state][:emulation :"sequential logic"]
[55:48][Check out our linearized Example38 to see the next state][:emulation :"sequential logic" :run]
[56:14][Implement register reading to pull in the next state][:"sequential logic"]
[58:41][Try to compile Example38][:"code generation" :"sequential logic" :run]
[59:48][Add tick() and reset() to the compile_template for compile() to emit][:"code generation" :"sequential logic"]
[1:03:49][Check out the generated code of Example38, to see that it looks reasonable][:"code generation" :"sequential logic" :run]
[1:04:57][Create a simulation test of our stateful Example38][:emulation :"sequential logic"]
[1:07:24][:Run the Example38 simulation to see the expected results][:emulation :"sequential logic"]
[1:08:30][Conveniently interacting with stateful circuits][:emulation :"sequential logic" :speech]
[1:09:39][Set up to make iterable instances of Example38][:emulation :"sequential logic"]
[1:11:39][Spec out an __iter__() function for Example38][:emulation :"sequential logic" :speech]
[1:13:00][Define SimulatorInstance class][:emulation :"sequential logic" :speech]
[1:18:28][Simulate our stateful instances successfully][:emulation :"sequential logic" :run]
[1:20:03][A few words on our iterable instances abstraction][:emulation :"sequential logic" :speech]
[1:21:33][Change our SimulatorInstance to reset on creation][:emulation :"sequential logic"]
[1:22:20][Check the code for Example38][:"code generation" :"sequential logic" :run]
[1:23:39][Reflect on our newly synchronous system][:emulation :"sequential logic" :speech]
[1:24:45][Set up to create interesting stateful circuits][:"sequential logic" :speech]
[1:25:13][Bit-serial multiplier][:"sequential logic" :speech]
[1:26:35][Spec out a bit-serial multiplier][:"sequential logic" :speech]
[1:28:41][Define Example39 as a bit-serial multiplier][:"sequential logic"]
[1:31:41][Check the graph of Example39][:"debug visualisation" :"sequential logic" :run]
[1:32:06][Create a simulation test of our bit-serial multiplier][:emulation :"sequential logic"]
[1:35:51][Simulate the bit-serial multiplier to see that it actually seems correct][:emulation :"sequential logic" :run]
[1:37:38][Test our bit-serial multiplier][:emulation :"sequential logic"]
[1:38:15][Simulate the bit-serial multiplier and fail the test][:emulation :"sequential logic" :run]
[1:38:55][Fix our bit-serial multiplier test][:emulation :"sequential logic"]
[1:39:05][Simulate the bit-serial multiplier, fail the test and investigate why][:emulation :"sequential logic" :run]
[1:44:05][Try printing our product beside the result of Python's own multiplication AND'd with the mask][:emulation :"sequential logic" :run]
[1:45:49][Make our bit-serial multiplier simulation perform one more iteration, to pass the test][:emulation :"sequential logic" :run]
[1:46:25][Reflect on our bit-serial multipler][:emulation :"sequential logic" :speech]
[1:46:58][Create a faster version of our bit-serial multiplier using a p_valid_reg control signal][:emulation :"sequential logic"]
[1:50:44][Simulate our faster bit-serial multiplier, fail the test and investigate why][:emulation :"sequential logic" :run]
[1:51:17][Change our bit-serial multiplier simulation not to check p_valid on the first iteration][:emulation :"sequential logic"]
[1:52:06][Simulate our faster bit-serial multiplier, fail the test again and continue to investigate why][:emulation :"sequential logic" :run]
[1:54:58][Check out the outputs of our bit-serial multiplier instances][:emulation :"sequential logic" :run]
[1:55:37][Rework our bit-serial multiplier simulation][:emulation :"sequential logic"]
[1:57:34][Simulate our faster bit-serial multiplier successfully][:emulation :"sequential logic" :run]
[1:58:07][Spec out some test code we'd like our co-routine interface to allow][:emulation :"sequential logic" :speech]
[2:00:00][Introduce simulate_test()][:emulation :"sequential logic"]
[2:03:06][Introduce example39_test() to test our simulate_test()][:emulation :"sequential logic"]
[2:05:11][:Run our simulate_test() successfully on example39_test()][:emulation :"sequential logic"]
[2:05:38][Reflect on our co-routine interface][:emulation :"sequential logic" :speech]
[2:07:20][We are done for that, with a glimpse into the future of state machine composition][:"sequential logic" :speech]
[/video]
