Annotate bitwise051

pervognsen/bitwise/bitwise/bitwise051.hmml

@@ -0,0 +1,66 @@
+[video member=pervognsen stream_platform=twitch project=bitwise title="Logic Design, Part 3" vod_platform=youtube id=T1GaWWgmoIQ annotator=Miblo]
+[0:01][Recap and set the stage for the day][:speech]
+[1:17][Consider the balanced reduction tree of our XOR circuit][:"debug visualisation" :"logic design" :run]
+[1:46][Associativity][:"logic design" :speech]
+[2:53][Delay and circuit depth][:"debug visualisation" :"logic design" :run]
+[3:40][Compare the linearly- and logarithmically-reduced XOR circuit][:"debug visualisation" :"logic design" :run]
+[6:19][Demo minimum_delay_reduce() which changes the order in which elements are combined][:"debug visualisation" :"logic design" :run]
+[9:44][How minimum_delay_reduce() works][:"logic design" :research]
+[11:54][@xanatos387][Is that based on the length of the trace, or something else?][:"logic design"]
+[14:10][@rygorous][@xanatos387 The source of the delay is that, in general, other signals are not immediately available: they come out of other combinatorial circuits. So you care about the total delay since the last flip-flop (or similar)][:"logic design"]
+[14:36][Simulation and :language processing][:emulation :speech]
+[17:26][How modules are defined][:language :"logic design" :research]
+[20:16][Set up to define a Copier Visitor for all our node types][:language :"logic design" :speech]
+[24:46][Handling cycles][:"graph topology" :"logic design" :speech]
+[26:50][Define UnaryNode() and InputNode() Copier][:"logic design"]
+[29:29][Trigger a "Cyclic node graph" error][:"logic design"]
+[30:07][Enable the UnaryNode Copier to handle cycles][:"graph topology" :"logic design"]
+[32:03][:Run it to see that it now works without error][:"graph topology" :"logic design"]
+[33:04][Make all the node initialisers take a type, rather than inferring it][:"logic design"]
+[37:23][Define ConstantNode(), BinaryNode(), CompareNode() and OutputNode() Copiers][:"logic design"]
+[39:45][Define InstanceInputNode(), InstanceOutputNode() and Module() Copiers][:"logic design"]
+[46:05][Define ConcatNode(), IndexNode(), SliceNode() and WhenNode() Copiers][:"logic design"]
+[50:13][Create Test module, define a set() Copier and introduce copy_module() and make_module()][:"logic design"]
+[58:11][Test copy_module()][:"logic design"]
+[1:01:45][:Run it to see our module-level copy][:"debug visualisation" :"logic design"]
+[1:02:05][Create ModuleInliner()][:"logic design"]
+[1:15:06][Introduce inline_module() and inline_top_module()][:"logic design"]
+[1:20:47][Test inline_top_module() to see that it works][:"debug visualisation" :"logic design" :run]
+[1:21:13][Create Xor module for our Test to use][:"logic design"]
+[1:22:15][:Run it to see our encapsulated Xor sub-module][:"debug visualisation" :"logic design"]
+[1:22:25][Break into ModuleInliner and step through to InstanceOutputNode until realising that we need a default handler][:"logic design" :run]
+[1:23:52][Define a default handler in ModuleInliner][:"logic design"]
+[1:25:00][Continue to step through ModuleInliner to see that it seemed to work][:"logic design" :run]
+[1:27:47][Consult our graph to see that it isn't right][:"debug visualisation" :"logic design" :run]
+[1:28:36][Change inline_module to return the output operand (not the node)][:"logic design"]
+[1:29:32][Consult our graph to see that it worked][:"debug visualisation" :"logic design" :run]
+[1:29:44][@recursivechat][A def can have an __init__?][:language]
+[1:30:34][@0b0000000000000][Can the other x and y inputs be removed?][:"logic design"]
+[1:30:50][Consider how to prevent the original top-level inputs from being copied][:"logic design" :speech]
+[1:32:54][Step through ModuleInliner to see what's happening with the original inputs][:"logic design" :run]
+[1:36:24][Dive into Test2 and determine that the inputs are not related to the ones that are externally hooked up][:"logic design" :run]
+[1:40:27][Note that the input duplication is only related to the sub-module][:"debug visualisation" :"logic design" :run]
+[1:41:01][Change the Module() Copier to put the copied self(node) - as opposed to the original node - into the instance_inputs array][:"logic design"]
+[1:41:11][:Run it to see that that fixed it][:"debug visualisation" :"logic design"]
+[1:42:13][Create an And module for our Xor to use, and so test sub-module inlining][:"logic design"]
+[1:43:39][:Run it to see that that works, and reflect on the simplicity of our Copier][:"debug visualisation" :"logic design"]
+[1:45:02][Create CyclicTest module torture test][:"logic design"]
+[1:47:45][:Run it to see our cycle][:"debug visualisation" :"logic design"]
+[1:48:13][Test inlining the CyclicTest, hit a "Cyclic node graph" error and consider how to resolve it][:"logic design"]
+[1:51:12][Create WireNode][:"logic design"]
+[1:54:02][Test WireNode][:"logic design"]
+[1:55:25][:Run it and explain the idea behind wires][:"debug visualisation" :"logic design"]
+[1:56:07][Make the InstanceOutputNode() ModuleInliner use wires, and define a WireNode() Copier][:"logic design"]
+[1:57:30][:Run it on Test2 to see that nothing broke][:"debug visualisation" :"logic design"]
+[1:58:20][:Run it on CyclicTest and see that the wires don't resolve our "Cyclic node graph" error][:"logic design"]
+[2:00:39][Simplify the InstanceOutputNode() Copier and make the Module() Copier create temporary wires][:"logic design"]
+[2:04:14][Step through the Copier to see how it all handles CyclicTest][:"logic design" :run]
+[2:04:58][Change the Module() Copier to put the output items (rather than the connections) as wires into the instance_outputs array][:"logic design"]
+[2:05:24][Continue to step through the Copier][:"logic design" :run]
+[2:08:13][Change the Module() Copier to put all the result.items() into the instance_outputs array][:"logic design"]
+[2:08:54][:Run it to see that our cyclic module works][:"debug visualisation" :"logic design"]
+[2:09:03][:Run it to see that our inlined cyclic module also works][:"debug visualisation" :"logic design"]
+[2:09:26][Create WireRemover using a newly introduced remove_wires()][:"logic design"]
+[2:10:54][Test remove_wires() to see that that works too][:"debug visualisation" :"logic design" :run]
+[2:11:58][Wind it down with a mention of the After Hours streams][:speech]
+[/video]