Annotate bitwise060

pervognsen/bitwise/bitwise/bitwise060.hmml

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+[video member=pervognsen stream_platform=twitch project=bitwise title="More FIFOs" vod_platform=youtube id=AJOVPv4P5nY annotator=Miblo]
+[0:07][Recap and set the stage for the day continuing with :"sequential logic"][:speech]
+[0:42][Review the off-stream bug-fix in the memory(), establishing read-after-write semantics][:memory :research :"sequential logic"]
+[3:05][Review the off-stream bug-fix in fifo(), establishing registered output][:memory :research :"sequential logic"]
+[7:25][Simulate our FIFO with the fifo_test_consumer() starting with idle cycles][:emulation :memory :run :"sequential logic"]
+[8:20][Set up to cover a shift register-based FIFO implementation useful in Xilinx FPGAs][:memory :"sequential logic" :speech]
+[10:10][Shift register][:"sequential logic" :speech]
+[11:00][Introduce shift_memory()][:memory :"sequential logic"]
+[14:09][Shifting sequential cells][:memory :"sequential logic" :speech]
+[15:11][Continue to implement shift_memory()][:memory :"sequential logic"]
+[17:54][Write a test of our shift :memory][:emulation :"sequential logic"]
+[20:48][Simulate our shift :memory successfully][:emulation :run :"sequential logic"]
+[21:46][Establish read-after-write semantics in shift_memory()][:memory :"sequential logic"]
+[23:09][Simulate our shift :memory successfully][:emulation :run :"sequential logic"]
+[23:29][Write a second test of our shift :memory that reads in the first element before shifting in a new value][:emulation :"sequential logic"]
+[24:55][Simulate our shift :memory successfully][:emulation :run :"sequential logic"]
+[25:05][Shift register-based FIFO][:memory :"sequential logic" :speech]
+[29:42][Introduce shift_fifo(), renaming fifo() to ring_fifo()][:memory :"sequential logic"]
+[38:47][Test our shift FIFO][:emulation :memory :"sequential logic"]
+[39:19][Simulate our shift FIFO test and hit a TypeError, Inconsistent types][:emulation :memory :run :"sequential logic"]
+[39:32][Make shift_fifo() explicitly compute the length][:memory :"sequential logic"]
+[40:54][Simulate our shift FIFO and step through to see what's taking it so long][:emulation :memory :run :"sequential logic"]
+[45:00][Fix the length computation in shift_fifo()][:memory :"sequential logic"]
+[45:57][Simulate our shift FIFO successfully][:emulation :memory :run :"sequential logic"]
+[46:20][Start fifo_test_consumer() with 100 idle cycles][:emulation :memory :"sequential logic"]
+[46:24][Simulate our shift FIFO with the fifo_test_consumer() starting with idle cycles][:emulation :memory :run :"sequential logic"]
+[46:46][Prevent shift_fifo() from filling up completely][:memory :"sequential logic"]
+[47:07][Simulate our shift FIFO successfully][:emulation :memory :run :"sequential logic"]
+[47:50][Establish registered outputs in shift_fifo()][:memory :"sequential logic"]
+[48:13][Simulate our shift FIFO with registered outputs successfully][:emulation :memory :run :"sequential logic"]
+[49:21][Block RAM in Xilinx FPGAs[ref
+    author=Xilinx
+    title="7 Series FPGAs Memory Resources"
+    url=https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf]][:hardware :memory :research]
+[51:00][The basic logic building block in Xilinx: a 6-input 1-output bit lookup table[ref
+    author=Xilinx
+    title="7 Series FPGAs Configurable Logic Block"
+    url=https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf]][:hardware :"logic design" :research]
+[54:37][The downside of building large FIFOs with shift registers][:memory :"sequential logic" :speech]
+[56:41][Valid / ready signaling[ref
+    author="UC Berkeley College of Engineering: Department of Electrical Engineering and Computer Science"
+    title="EECS150: Interfaces: \"FIFO\" (a.k.a. Ready/Valid)"
+    url=https://inst.eecs.berkeley.edu/~cs150/Documents/Interfaces.pdf]][:memory :research :"sequential logic"]
+[1:02:57][Introduce chain_fifo()][:memory :"sequential logic"]
+[1:10:23][Write a test of our chain FIFO][:emulation :memory :"sequential logic"]
+[1:13:17][Simulate our chain FIFO to find that it is successfully enqueueing, but slow][:emulation :memory :run :"sequential logic"]
+[1:14:55][Simulate it from the command line, hopefully for speed][:emulation :memory :run :"sequential logic"]
+[1:17:19][Simulate it with smaller FIFOs][:emulation :memory :run :"sequential logic"]
+[1:18:28][Investigate why the chain_fifo() isn't getting the message that the producer has finished][:emulation :memory :research :"sequential logic"]
+[1:19:30][Fix chain_fifo() to correctly dequeue][:memory :"sequential logic"]
+[1:22:31][Simulate the size 2 chain FIFO and watch what it does][:emulation :memory :run :"sequential logic"]
+[1:24:31][Simulate a size 3 chain FIFO, also successfully][:emulation :memory :run :"sequential logic"]
+[1:24:46][Simulate a size 4 chain FIFO, unsuccessfully, and step through chain_fifo()][:emulation :memory :run :"sequential logic"]
+[1:27:33][Check the graph of a size 4 chain FIFO][:"debug visualisation" :memory :run :"sequential logic"]
+[1:30:11][Investigate the possibility that we have a latent delay-related bug][:emulation :memory :run :"sequential logic"]
+[1:34:32][Scrutinise the graph of a size 4 chain FIFO][:"debug visualisation" :memory :run :"sequential logic"]
+[1:35:33][Scrutinise the code of chain_fifo()][:memory :research :"sequential logic"]
+[1:37:08][Call it a day, with another recommendation of UC Berkeley's 'Interfaces: "FIFO" (a.k.a. Ready/Valid)'[ref
+    author="UC Berkeley College of Engineering: Department of Electrical Engineering and Computer Science"
+    title="EECS150: Interfaces: \"FIFO\" (a.k.a. Ready/Valid)"
+    url=https://inst.eecs.berkeley.edu/~cs150/Documents/Interfaces.pdf] and a glimpse into the future][:memory :"sequential logic" :speech]
+[/video]