Annotate riscy/reader004
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Matt Mascarenhas
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[video member=miotatsu stream_platform=twitch project=book title="2.4-2.5" vod_platform=youtube id=SdIJjDvEkcs annotator=Miblo]
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[0:01][Recap and set the stage for the day][:speech]
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[1:49][Review where we're at]
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[2:27][Chapter 2.4 - RV32I Integer Computation[ref
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title="RISC-V Reader"
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author="David Patterson and Andrew Waterman"
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publisher="Strawberry Canyon"
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isbn=9780999249116
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url=http://www.riscvbook.com/]][:isa]
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[3:43][A few words on the Spectre and Meltdown vulnerabilities due to branch-prediction and speculative execution][:performance :security :speech]
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[8:19][Chapter 2.4 continued[ref
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title="RISC-V Reader"
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author="David Patterson and Andrew Waterman"
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publisher="Strawberry Canyon"
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isbn=9780999249116
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url=http://www.riscvbook.com/]][:isa]
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[10:08][Point out the mistake in the book's description of the "call" pseudo-instruction[ref
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title="RISC-V Reader"
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author="David Patterson and Andrew Waterman"
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publisher="Strawberry Canyon"
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isbn=9780999249116
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url=http://www.riscvbook.com/]][:isa :speech]
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[13:30][Chapter 2.4 continued, on RISC-V's simple arithmetic instructions[ref
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title="RISC-V Reader"
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author="David Patterson and Andrew Waterman"
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publisher="Strawberry Canyon"
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isbn=9780999249116
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url=http://www.riscvbook.com/]][:isa :mathematics]
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[16:47][A few words of praise for the concision of the RISC-V base :ISA][:blackboard]
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[19:36][Plug [@cmuratori Casey]'s Meow hash,[ref
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site="Twitter: @cmuratori"
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page="Introducing the Meow hash - a non-cryptographic hash capable of 16 bytes _per cycle_ throughput on modern CPUs while still cleanly passing all of smhasher"
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url=https://twitter.com/cmuratori/status/1053453319299977221][ref
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site="Molly Rocket"
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page="Meow Hash"
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url=https://mollyrocket.com/meowhash] [@mmozeiko Mārtiņš]'s ports to ARMv8[ref
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site="Twitter: @mmozeiko"
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page="Meow hash for ARMv8"
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url=https://twitter.com/mmozeiko/status/1054786688361279490] and C without special hardware instructions,[ref
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site="Twitter: @mmozeiko"
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page="Meow hash in generic C"
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url=https://twitter.com/mmozeiko/status/1054942982099496960] and @Miblo's plea for a RISC-V port[ref
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site="Twitter: @miblo_"
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page="RISC-V next, @miotatsu?"
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url=https://twitter.com/miblo_/status/1054800216371707904] which @miotatsu will happily contribute[ref
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site="Twitter @miotatsu"
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page="I will happily contribute a RISC-V version when the standard crypto extension proposal is accepted/publicly documented - Meow is built around having AES in hardware"
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url=https://twitter.com/miotatsu/status/1054894248603148293] once RISC-V gets the proposed vector and crypto extensions[ref
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author="G. Richard Newell"
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title="Using Proposed Vector and Crypto Extensions For Fast and Secure Boot"
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url=https://content.riscv.org/wp-content/uploads/2017/12/Wed-1418-RISCV-RichardNewell.pdf]][:hashing :isa :language]
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[37:01][Chapter 2.4 continued, on RISC-V's comparison and branching instructions[ref
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title="RISC-V Reader"
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author="David Patterson and Andrew Waterman"
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publisher="Strawberry Canyon"
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isbn=9780999249116
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url=http://www.riscvbook.com/]][:isa]
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[39:15][Summarise the concept of auipc and jal to allow for 32-bit immediates][:blackboard :isa]
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[46:16][Figure 2.4 - The registers of RV32I[ref
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title="RISC-V Reader"
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author="David Patterson and Andrew Waterman"
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publisher="Strawberry Canyon"
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isbn=9780999249116
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url=http://www.riscvbook.com/][ref
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site=RISC-V
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page="User-Level ISA Specification v2.2"
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url=https://riscv.org/specifications]][:isa]
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[52:27][Chapter 2.4 continued, on the differences between RISC-V and ARM[ref
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title="RISC-V Reader"
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author="David Patterson and Andrew Waterman"
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publisher="Strawberry Canyon"
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isbn=9780999249116
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url=http://www.riscvbook.com/]][:isa]
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[55:36][Chapter 2.4 Elaboration 1 - "Bit twiddling" instructions[ref
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title="RISC-V Reader"
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author="David Patterson and Andrew Waterman"
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publisher="Strawberry Canyon"
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isbn=9780999249116
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url=http://www.riscvbook.com/]][:isa]
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[55:54][Chapter 2.4 Elaboration 2 - xor enables a magic trick[ref
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title="RISC-V Reader"
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author="David Patterson and Andrew Waterman"
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publisher="Strawberry Canyon"
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isbn=9780999249116
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url=http://www.riscvbook.com/]][:isa :mathematics]
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[59:47][XOR swap, thanks to algebraic reversibility][:blackboard :mathematics]
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[1:19:12][Chapter 2.4 Elaboration 2 continued[ref
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title="RISC-V Reader"
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author="David Patterson and Andrew Waterman"
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publisher="Strawberry Canyon"
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isbn=9780999249116
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url=http://www.riscvbook.com/]][:isa :mathematics]
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[1:21:54][XOR linked list, again thanks to algebraic reversibility[ref
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site=Wikipedia
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page="XOR swap algorithm"
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url=https://en.wikipedia.org/wiki/XOR_swap_algorithm][ref
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site=Wikipedia
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page="XOR linked list"
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url=https://en.wikipedia.org/wiki/XOR_linked_list]][:blackboard :"data structure"]
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[1:43:36][Chapter 2.5 - RV32I Loads and Stores[ref
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title="RISC-V Reader"
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author="David Patterson and Andrew Waterman"
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publisher="Strawberry Canyon"
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isbn=9780999249116
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url=http://www.riscvbook.com/]][:isa :memory]
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[1:46:23][Recommend [@rygorous Fabian]'s videos on CPU µArch[ref
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site=YouTube
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page="Fabian Giesen"
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url=https://www.youtube.com/channel/UCcRaa0AcYX32c0m8wJJHNWg/videos]][:isa]
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[1:50:55][Chapter 2.5 continued, on differences in load / store instruction between RISC-V and MIPS and ARM[ref
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title="RISC-V Reader"
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author="David Patterson and Andrew Waterman"
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publisher="Strawberry Canyon"
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isbn=9780999249116
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url=http://www.riscvbook.com/]][:isa]
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[1:51:52][Recommend [@babbageboole Robert Baruch]'s LMARV-1 video series[ref
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site=YouTube
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page=LMARV-1
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url=https://www.youtube.com/playlist?list=PLEeZWGE3PwbansoxKjjMKHQqS_2cm8i60]][:isa]
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[1:53:23][Chapter 2.5 Elaboration - Endianness[ref
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title="RISC-V Reader"
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author="David Patterson and Andrew Waterman"
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publisher="Strawberry Canyon"
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isbn=9780999249116
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url=http://www.riscvbook.com/]][:isa :memory]
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[1:55:27][Endianness from Gulliver's Travels[ref
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site=Wikipedia
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page="Gulliver's Travels"
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url=https://en.wikipedia.org/wiki/Gulliver%27s_Travels]]
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[1:59:19][That's the end of 2.5][:speech]
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[1:59:59][@krish2nasa][I missed this episode]
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[2:02:06][Endianness in practice in pcalc[ref
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site=GitLab
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page="pcalc"
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url=https://gitlab.com/riscy-business/pcalc]][:memory]
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[2:02:18][@krish2nasa][I have a question for you: Is hamming distance implemented in RISC-V :ISA and the compiler for more energy / code efficiency?]
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[2:05:31][Endianness in practice in pcalc continued,[ref
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site=GitLab
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page="pcalc"
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url=https://gitlab.com/riscy-business/pcalc] including connecting to an X11 server using the \~/.Xauthority file][:memory]
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[2:12:05][End the episode there][:speech]
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[/video]
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