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Annotate bitwise023

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Matt Mascarenhas 2018-05-10 23:13:41 +01:00
parent 070993b823
commit 2a9403a298
2 changed files with 56 additions and 2 deletions
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56
pervognsen/bitwise/bitwise/bitwise023_1.hmml
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[video member=pervognsen stream_platform=twitch project=bitwise title="RISC-V Toolchain Implementation" vod_platform=youtube id=zDOd3inaOsY annotator=Miblo]
[0:00][\[Annotations to be written…\]]
[0:09][Recap and set the stage for the day, with a note that off-stream work will now be covered in write-ups, rather than on stream][:speech]
[2:05][Plan to create two tools: assembler and simulator][:isa :speech]
[5:44][Chapter 19 - RV32/64G Instruction Set Listings[ref
author="Andrew Waterman and Krste Asanović"
title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa :research]
[8:05][Dive into writing our RISC-V assembler, starting with an Instruction struct[ref
author="Andrew Waterman and Krste Asanović"
title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[13:30][Introduce decode_instruction() and encode_instruction() and declare our immediate field masks[ref
author="Andrew Waterman and Krste Asanović"
title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[20:47][Add cases for LUI, AUIPC, JAL, JALR and the branch instructions in decode_instruction()[ref
author="Andrew Waterman and Krste Asanović"
title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[35:45][Introduce empty decode_u_instruction(), decode_j_instruction(), decode_b_instruction() and decode_i_instruction()][:isa]
[36:21][Look into handling the "'riscv_Op': undeclared identifier" error]
[38:54][Just disable typeinfo for now][:admin]
[39:36][Add cases for the load and store instructions in decode_instruction(), also introducing an empty decode_s_instruction()[ref
author="Andrew Waterman and Krste Asanović"
title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[44:27][Add a case for the integer register-immediate instructions in decode_instruction()[ref
author="Andrew Waterman and Krste Asanović"
title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[58:57][Add a case for the FENCE / FENCE.I instructions in decode_instruction()[ref
author="Andrew Waterman and Krste Asanović"
title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[1:00:38][Enable Ion's scan_int() to skip _ delimiters in int declarations][:parsing]
[1:03:26][Finish up the FENCE / FENCE.I case in decode_instruction()[ref
author="Andrew Waterman and Krste Asanović"
title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[1:09:00][Add a case for the integer register-register instructions in decode_instruction()[ref
author="Andrew Waterman and Krste Asanović"
title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[1:18:27][Add a case for the environment call and breakpoints instructions ECALL and EBREAK in decode_instruction()[ref
author="Andrew Waterman and Krste Asanović"
title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[1:22:25][Include the CSR (Control and Status Register) instructions in the ECALL / EBREAK case in decode_instruction(), introducing decode_csr_instruction()[ref
author="Andrew Waterman and Krste Asanović"
title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[1:25:35][Reflect on the day's work][:speech]
[1:26:55][Q&A][:speech]
[1:28:03][@arbitraryslayer][Hi @pervognsen, I have a quick question. Why do you think C is preferred over C++ for system level when C++ has more features than C?][:language]
[1:29:11][@nothings2][Also I wonder if bitfields would make instruction decoding cleaner][:language]
[1:29:51][Cut over to the extra stream][:speech]
[/video]

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pervognsen/bitwise/bitwise/bitwise023_2.hmml
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[video member=pervognsen stream_platform=twitch project=bitwise title="RISC-V Toolchain Implementation (Extra)" vod_platform=youtube id=kRmvjEpziuM annotator=Miblo]
[0:00][\[Entire stream, not annotated\]]
[0:00][\[Entire stream, not annotated\]][:isa]
[/video]