From 380a7a9b082fb941ceae2c01aa573e92ae57f333 Mon Sep 17 00:00:00 2001 From: Matt Mascarenhas Date: Thu, 21 Dec 2017 18:48:43 +0000 Subject: [PATCH] Annotate riscy054 --- miotatsu/riscy/riscy/riscy054.hmml | 48 ++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 miotatsu/riscy/riscy/riscy054.hmml diff --git a/miotatsu/riscy/riscy/riscy054.hmml b/miotatsu/riscy/riscy/riscy054.hmml new file mode 100644 index 0000000..4c454f6 --- /dev/null +++ b/miotatsu/riscy/riscy/riscy054.hmml @@ -0,0 +1,48 @@ +[video member=miotatsu stream_platform=twitch project=riscy title="pwm_speed_test refresher & handle_trap" vod_platform=youtube id=QqZUw1Xiofk annotator=Miblo] +[0:08][Recap and set the stage for the day][:speech] +[0:46][Reacquaint ourselves with pwm_speed_test.c][:profiling :research] +[8:36][Compile pwm_speed_test[ref + site="SiFive Developers" + page="SiFive HiFive1 Getting Started Guide" + url=https://static.dev.sifive.com/dev-kits/hifive1/hifive1-getting-started-v1.0.3.pdf] and recall that the program didn't do what we want] +[11:32][Consult the annotations for days 049 and 050 to see how we got where we did][:research] +[20:30][Learn how mei_isr() is setup in global_interrupts.c][:research] +[23:33][Read 3.1.12 - Machine Trap Delegation Registers (medeleg and mideleg)[ref + site="RISC-V" + page="Draft Privileged ISA Specification v1.9.1" + url=https://riscv.org/specifications/privileged-isa/] with mentions of hypervisor mode as used in Xen[ref + site=Wikipedia + page=Xen + url=https://en.wikipedia.org/wiki/Xen] and Qubes OS[ref + site=Wikipedia + page="Qubes OS" + url=https://en.wikipedia.org/wiki/Qubes_OS]][:research] +[33:32][Continue to read 3.1.12[ref + site="RISC-V" + page="Draft Privileged ISA Specification v1.9.1" + url=https://riscv.org/specifications/privileged-isa/] with a mention of RISC-V based real-time software[ref + site="RISC-V Foundation" + page="Software Status" + url=https://riscv.org/software-status/]][:research] +[37:21][Scan through the other documentation for chip specifications of privilege modes][:research] +[41:02][Continue to read 3.1.12 about trap delegation[ref + site="RISC-V" + page="Draft Privileged ISA Specification v1.9.1" + url=https://riscv.org/specifications/privileged-isa/]][:research] +[45:46][Read 3.1.11 - Machine Trap-Vector Base-Address Register (mtvec)[ref + site="RISC-V" + page="Draft Privileged ISA Specification v1.9.1" + url=https://riscv.org/specifications/privileged-isa/] with a moment of realisation as to why we do .align 2][:research] +[50:57][Show the RISC-V Reader and plug the stream schedule[ref + site=Twitter + page="@hmn_riscy: I'm going to be trying the following stream schedule (Mon-Fri): 09:00-14:00 CST: Programming 14:00-15:00 CST: RISCY BUSINESS 15:00-17:00 CST: Games" + url=https://twitter.com/hmn_riscy/status/935267027404587008]][:speech] +[54:41][Continue to read 3.1.11 on implementation-specific trap handlers[ref + site="RISC-V" + page="Draft Privileged ISA Specification v1.9.1" + url=https://riscv.org/specifications/privileged-isa/]][:research] +[58:46][Study the trap handling code in the Freedom E SDK and Coreplex IP E31 Arty][:research] +[1:04:45][pwm_speed_test.c: Call write_csr() and introduce handle_trap()] +[1:11:50][Commit "Day 54"][:admin] +[1:13:08][End it here][:speech] +[/video]