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+[video member=pervognsen stream_platform=twitch project=bitwise title="Logic Design, Part 4" vod_platform=youtube id=n4ALQT60SqY annotator=Miblo]
+[0:00][Recap and set the stage for the day][:speech]
+[0:32][Refresh our memories on module inlining][:"debug visualisation" :"logic design" :research :run]
+[3:04][Review the addition of the generic OperatorNode][:"logic design" :research]
+[5:35][Hope to get to shifters, but determine first to get a simulator working][:"logic design" :emulation :speech]
+[6:27][The plan for the simulator][:"logic design" :emulation :speech]
+[7:33][Determine to prepend a prefix to the names of inlined nodes][:"logic design" :speech]
+[9:01][Make ModuleInliner prepend the name of inlined nodes with that of the instance][:"logic design"]
+[13:26][:Run it to see our prefixed node names][:"debug visualisation" :"logic design"]
+[13:39][Enable the Cyclic module to handle modules contained in other structures, and change ModuleInliner to use the original, not lowered, name][:"logic design"]
+[15:08][:Run it to see our unadulterated module class name][:"debug visualisation" :"logic design"]
+[15:18][@spriithy][Anyways bye, it's like 3am here]
+[15:37][Set up to start work on the simulator as a compiler][:emulation :language :speech]
+[18:54][Define Linearizer Visitor, noting down the nodes it'll need to handle][:"logic design"]
+[22:34][Create InputNode() Linearizer, introducing make_temp() and instruction()][:"logic design"]
+[26:24][Create OutputNode(), OperatorNode(), IndexNode(), SliceNode(), ConstantNode() and WireNode() Linearizers][:"logic design"]
+[33:03][Introduce linearize()][:"logic design"]
+[36:04][Test linearize() on Inv2][:"logic design"]
+[38:02][The influence of muscle memory on the switch from Python 2 to 3][:language :trivia]
+[38:22][Check out the result of our linearize()][:"logic design" :run]
+[38:41][More prettily print out the results of linearize()][:"logic design"]
+[39:58][@elavid][So who is this Mon, age 36?]
+[40:04][Fix up compile errors][:"logic design"]
+[40:28][Check out the more prettily printed result of our linearize()][:"logic design" :run]
+[40:49][Further prettify the printed result of linearize()][:"logic design"]
+[42:03][Check out the yet prettier printed result of our linearize()][:"logic design" :run]
+[42:27][Print the node names in lowercase][:"logic design"]
+[42:55][Consult the result of linearize(), to determine that it looks right][:"logic design" :run]
+[43:56][Compiling our linearized circuits, taking advantage of Python's arbitrary precision integers][:emulation :language :"logic design" :speech]
+[45:09][Generating IndexNode and SliceNode for bit vectors][:"logic design" :speech]
+[49:10][Bit concatenation][:"logic design" :speech]
+[52:27][Introduce compile()][:"code generation" :emulation :language :"logic design"]
+[1:12:38][Check out the results of compile()][:"code generation" :emulation :language :"logic design" :run]
+[1:12:56][Create CompilerTest module to test compile() with bit shifting][:"code generation" :emulation :language :"logic design"]
+[1:13:44][Check out the results of compile() on bit shifting][:"code generation" :emulation :language :"logic design" :run]
+[1:14:54][Add some slicing in CompilerTest, and fix compile() to initialise masks as a set][:"code generation" :emulation :language :"logic design"]
+[1:15:35][Check out the results of compile() on slicing][:"code generation" :emulation :language :"logic design" :run]
+[1:15:53][Make compile() prepend mask lines with "mask_"][:"code generation" :emulation :language :"logic design"]
+[1:17:00][Check out our prepended mask lines][:"code generation" :emulation :language :"logic design" :run]
+[1:17:18][Add multi-concatenation in CompilerTest][:"code generation" :emulation :language :"logic design"]
+[1:17:50][Check out the results of compile() on multi-concatenation][:"code generation" :emulation :language :"logic design" :run]
+[1:18:08][@binjimin][Could just use 0b11...11 for mask instead, right?]
+[1:19:11][Test operators in CompilerTest][:"code generation" :emulation :language :"logic design" :programming :run]
+[1:22:11][Test when() in CompilerTest][:"code generation" :emulation :language :"logic design"]
+[1:22:49][Check out the results of compile() on when()][:"code generation" :emulation :language :"logic design" :run]
+[1:23:25][The idea for compiling a module][:"code generation" :emulation :language :"logic design" :speech]
+[1:27:54][The idea behind a bundle][:"code generation" :emulation :language :"logic design" :speech]
+[1:28:44][Fix compile() to mask upon reading from an input][:"code generation" :emulation :language :"logic design"]
+[1:29:25][Bundles, continued][:"code generation" :emulation :language :"logic design" :speech]
+[1:31:23][Create compile_template[ref
+    site="Python 3.7.0 documentation"
+    page="6.1.4. Template strings"
+    url=https://docs.python.org/3/library/string.html#template-strings]][:"code generation" :emulation :language :"logic design"]
+[1:36:05][Enable compile() to indent and init the lines][:"code generation" :emulation :language :"logic design"]
+[1:40:53][Check out our indented and initialised lines][:"code generation" :emulation :language :"logic design" :run]
+[1:41:03][Make compile() evaluate the args, inputs and outputs, and perform substitutions][:"code generation" :emulation :language :"logic design"]
+[1:44:41][Fix all indentation][:"code generation" :emulation :language :"logic design"]
+[1:47:10][Check out our generated code][:"code generation" :emulation :language :"logic design" :run]
+[1:47:16][Enable compile() to execute its generated code, fixing the compile_template and code ordering][:"code generation" :emulation :language :"logic design" :run]
+[1:50:42][:Run it to see that it worked][:"code generation" :emulation :language :"logic design" :run]
+[1:51:05][Create a verifiable test in CompilerTest][:"code generation" :emulation :language :"logic design"]
+[1:51:54][:Run it and consider that it's not right][:"code generation" :emulation :language :"logic design"]
+[1:53:04][@binjimin][What's precedence of \@?][:language]
+[1:53:41][Fix our code.evaluate() call in compile() to determine that it totally works][:"code generation" :emulation :language :"logic design" :run]
+[1:54:20][Enable compile() to check the results itself][:"code generation" :emulation :language :"logic design"]
+[1:55:32][:Run it to see that it's pretty good][:"code generation" :emulation :language :"logic design"]
+[1:56:00][Stateful systems][:"code generation" :emulation :language :"logic design" :speech]
+[1:57:07][Consider the :performance of this simulator][:emulation :speech]
+[1:59:19][That's it for today, with a glimpse into the future going back to :"logic design"][:speech]
+[/video]