Annotate bitwise040

pervognsen/bitwise/bitwise/bitwise040.hmml

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+[video member=pervognsen stream_platform=twitch project=bitwise medium=speech title="How To Program Assembly Language" vod_platform=youtube id=SgVs93yYL44 annotator=Miblo]
+[0:08][Set the stage for the promised stream]
+[1:10][Disclaimer: Our handwritten assembly likely won't outperform an optimising compiler; writing assembly gives us a soft-intro to machine :"code generation"][:asm]
+[5:54][The approach we'll be taking, translating C to assembly][:asm :language]
+[7:27][Goal: Translate from C to assembly :language, with thoughts on variable width operations, and RISC-V as a compare-and-branch language][:asm :isa]
+[11:40][Idea: Gradually lower C towards target :language][:asm]
+[13:09][Example: Lowering a pointer increment from C to assembly, through a process of :language feature dependency removal][:asm :mathematics]
+[21:44][Features in C that may not be available in an assembly :language][:asm]
+[32:49][@elavid][More missing operations: modulo, floating point stuff, greater-than-or-equal][:asm :language]
+[32:56][More "missing" operations][:asm :language]
+[36:13][Local variables][:asm :language]
+[47:08][Smaller-than-word variables have to live in word-sized registers and use word-sized ops][:asm :language :mathematics]
+[53:38][Naively lowering an implicitly cast smaller-than-word arithmetic operation from C to assembly][:asm :language :mathematics]
+[1:02:56][A note on the pessimism of this conversion][:asm :language :mathematics]
+[1:05:17][Eliding zero / sign extension when working in architectures with sub-word store-to-memory operations, such as RISC-V][:asm :isa :language :mathematics]
+[1:11:43][@tomas99batista][Do you like assembly, @pervognsen?][:asm]
+[1:12:52][Operating on larger-than-word-sized data types][:asm :language :mathematics]
+[1:14:10][@xanatos387][How does this extend for 64-bit or 128-bit RISC-V variants? I assume you have to treat 32-bit :memory operations as sub-word and potentially even 64-bit operations. Trying to think that through. The instruction formats are the same. Is it possible to write "CPU 32 / 64 / 128-bit portable" RISC-V :ASM?][:isa]
+[1:14:38][4.2 Integer Computational Instructions[ref
+    author="Andrew Waterman and Krste Asanović"
+    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
+    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa :mathematics :research]
+[1:18:02][Architecture-specific larger-than-word-sized arithmetic operations, with and without a carry flag][:asm :language :isa :mathematics]
+[1:27:09][@elavid][Section 2.4 of the RISC-V instruction set has code for detecting overflow. Looks like it uses BLTU[ref
+    author="Andrew Waterman and Krste Asanović"
+    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
+    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
+[1:27:45][RISC-V MULH / MULHU multiply instructions][:isa :mathematics]
+[1:29:32][6.2 Division Operations[ref
+    author="Andrew Waterman and Krste Asanović"
+    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
+    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa :mathematics :research]
+[1:30:51][Summarise the topics covered][:asm]
+[1:31:41][@xanatos387][Kind of unfortunate to not be able to do a double-width arithmetic without a branch, though][:isa :mathematics]
+[1:33:06][@xanatos387][Since we're building our own, do you get tempted to "add" nonstandard missing operations?[ref
+    author="Andrew Waterman and Krste Asanović"
+    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
+    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
+[1:34:24][@captainpepperoni][Assembly is a lower level :language, right?][:asm]
+[1:34:55][That's it for today, with a glimpse into the future]
+[/video]