bitwise000: Credit comment authors

Thanks to @AsafGartner for the log

pervognsen/bitwise/bitwise/bitwise000.hmml

@@ -25,34 +25,34 @@
 [26:00][Feasibility, sustainability and burnout, and the phases of the project]
 [32:58][Next steps, starting on the compiler]
 [33:28][Q&A]
-[34:33][Do you have an idea of the kind of OS you will be making?][:authored]
+[34:33][@mistyr0se][@pervognsen Do you have an idea of the kind of OS you're going to be making? A Unix clone?]
-[36:41][You mention that fluency in C is a requirement. Presumably very little will be syntax dependent and you just mean fluency in systems level programming, and I'll just be able to coast by with fluency in Rust instead?][:authored :language]
+[36:41][@badcodeshane][@pervognsen You mentioned that fluency in C is a requirement. Presumably very little will be syntax dependent and you just mean "fluency in systems level programming", and I'll just be able to coast by with fluency in Rust instead?][:language]
-[37:37][For the compiler, are you going to use an existing RV32I emulator for testing?][:authored]
+[37:37][@godling72][@pervognsen For the compiler, are you going to use an existing RV32I emulator for testing?]
-[38:32][Have you looked at JAI from [@jon Jon Blow] very much?][:authored :language]
+[38:32][@c__jm][@pervognsen Have you looked at JAI from [@jon Jon Blow] very much?][:language]
-[39:47][Any specific reason to using Verilog over VHDL for compile target? VHDL seems to be a bit more popular with FPGAs][:authored :language]
+[39:47][@pragmascrypt][@pervognsen Any specific reason to using Verilog over VHDL for compile target? VHDL seems to be a bit more popular with FPGAs][:language]
-[40:45][Will you be supporting UEFI?][:authored :firmware]
+[40:45][@badcodeshane][@pervognsen Will you be supporting UEFI?][:firmware]
-[41:01][How long until I can write some small graphics demos for the computer, e.g. ray tracers? Would it be possible to get a max perf mode without :memory virtualisation page tables preemption?][:authored :rendering]
+[41:01][@pixelpoet][@pervognsen 0. How long until I can write some small graphics demos for the computer, e.g. ray tracers? 1. Would it be possible to get a "max performance" mode without :memory virtualisation / page tables, preemption?][:rendering]
-[42:25][Do you plan for the CPU and OS to be multicore?][:authored :hardware]
+[42:25][@onebloke][@pervognsen Do you plan for the CPU and OS to be multicore?][:hardware]
-[43:49][Really excited for this project! If you don't attend university, it's hard to break into things like compiler design and :firmware programming, so this could be a great resource for people who didn't go to university][:authored]
+[43:49][@badcodeshane][@pervognsen Can I just say how excited I am to see you kicking off this project? As someone who didn't attend university, it's hard to break into things like compiler design and :firmware programming, so this could be a great resource for people like myself to become acquainted with these more abstract, esoteric topics]
-[44:51][What's your personal timezone?][:authored :trivia]
+[44:51][@markajohnson][@pervognsen Not directly relevant to the content you're presenting, but what time zone are you in?][:trivia]
-[45:22][Do you intend to include the community in development, e.g. discussion groups on some interfaces, taking pull requests?][:authored]
+[45:22][@heroickatora][@pervognsen Do you intend to include the community in development, e.g. discussion groups on some interfaces, taking pull requests?]
-[47:45][What HDL will we use to create the CPU?][:authored :hardware :language]
+[47:45][@heasummn][What HDL will you be using to create the CPU?][:hardware :language]
-[48:44][As the project progresses do you foresee any problems with backwards compatibility, e.g. breaking changes for community-driven projects?][:authored]
+[48:44][@pmttavara][@pervognsen As the project progresses do you foresee any problems with backwards compatibility, e.g. breaking changes for community-driven projects?]
-[50:15][How long do you think the stream will go on for?][:authored]
+[50:15][@mistyr0se][@pervognsen How long do you think the stream will go on for?]
-[51:24][How do we support you?][:authored]
+[51:24][@filiadelski][@pervognsen How do we support you?]
-[53:25][How often will you stream, every day?][:authored]
+[53:25][@nyear][How often will you stream? Every day?]
-[54:05][Is the project supposed to be mimicking state-of-the-art but with corners cut, or just an example way to do things? For example, is the compiler planned with the SSAIR the way compilers seem to prefer, or more something like the Dragon Book?][:authored]
+[54:05][@jprzemieniecki][@pervognsen Is the project supposed to be mimicking state-of-the-art but with corners cut, or just an example way to do things? For example, is the compiler planned with the SSA IR the way compilers seem to prefer, or more like something from a dragon's book?]
-[57:16][By targeting a :hardware description :language, the OS will be virtualised, right? I'll be able to run it within VirtualBox or something similar?][:authored]
+[57:16][@badcodeshane][By targeting a :hardware description :language, the OS will be virtualised, right? I'll be able to run it within VirtualBox or something similar?]
-[58:38][Will you code your own DDR3 controller or will you use the FPGA's one?][:authored]
+[58:38][@pmttavara][@pervognsen Someone in discord asked: Will you code your own DDR3 controller or will you use the FPGA's one?]
-[59:38][You're on Windows. Can folks on Linux be assured to find these tools that are needed?][:authored]
+[59:38][@eddywm][You're on Windows. Can folks on Linux be assured to find these tools that are needed?]
-[1:00:48][I designed an SDRAM controller, but I had to add an additional cycle of latency. Do you have an oscilloscope to look at the :memory signals?][:authored]
+[1:00:48][@riskyfive][I designed an SDRAM controller for the Papilio Pro (Spartan 6 LX9), but I had to add an additional cycle of latency. Do you have an oscilloscope to look at the :memory signals?]
-[1:02:11][Audio issues][:authored]
+[1:02:11][@symbolic_butt][@pervognsen I just came in, sorry if this was said before but the sound is super low]
-[1:02:31][Have you already decided what FPGA will be used?][:authored :hardware]
+[1:02:31][@doomguyfieri][Have you already decided what FPGA will be used, or is that a decision that will be made later?][:hardware]
-[1:03:24][You can actually rent high-end oscilloscopes on a short-term basis][:authored]
+[1:03:24][@nuttynutnutnutter][@pervognsen You can rent high-end oscilloscopes on a short-term basis, if necessary]
-[1:04:03][Will you stick around in the chat after the Q&A?][:authored]
+[1:04:03][@badcodeshane][Will you be going offline after the Q&A or getting started?]
-[1:04:24][Did you use high-end oscilloscopes at Occulus][:authored]
+[1:04:24][@godling72][@pervognsen The non high-end oscilloscope version would be educational]
-[1:05:37][Will we cover printed circuit design?][:authored :hardware]
+[1:05:37][@nuttynutnutnutter][@pervognsen: Maybe you mentioned it (I missed the first \~30 minutes of the stream), but it sounds like you're going to be doing a PCB design also? If so, Kicad, Altium, OrCad, Eagle, etc?][:hardware]
-[1:06:14][Are FPGAs considered for prototyping or is it meant to be used in finished products?][:authored :fabrication :hardware]
+[1:06:14][@jim0_o][@pervognsen I don't know much about FPGAs so I wonder, is it considered something for prototyping or is it meant to be used in finished products?][:fabrication :hardware]
-[1:08:59][Would you consider doing an upfront brain-dump doc of some of the references, books and such that you found worth the time related to the topics within the scope of the project?][:authored]
+[1:08:59][@kryu][@pervognsen Would you consider doing an upfront brain-dump doc of some of the references, books and such, that you've found worth the time related to the topics within the scope of the project?]
 [1:09:45][Stop the stream now]
 [/video]