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Matt Mascarenhas 2018-08-05 19:54:13 +01:00
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[video member=pervognsen stream_platform=twitch project=bitwise title="Logic Design, Part 8" vod_platform=youtube id=SHgW5PM4R6w annotator=Miblo]
[0:08][Set the stage for the day covering dividers][:"logic design" :speech]
[1:48][A quick note on the streaming schedule from Denmark][:speech]
[2:56][Note our use of CPython, and consider switching to PyPy for improved :performance][:language :speech]
[4:13][Review our multipliers][:"logic design" :research]
[8:36][Set up to cover dividers][:"logic design" :speech]
[10:26][Integer division][:"logic design" :speech]
[13:45][Euclidean algorithm (division by repeated subtraction)][:"logic design" :speech]
[17:17][Long division (finish one digit of the quotient per iteration)][:"logic design" :speech]
[24:50][Introduce euclidean_divide() as a software routine][:"logic design"]
[25:59][Introduce binary_divide() as a software routine][:"logic design"]
[27:47][Test euclidean_divide() to see that it works][:"logic design" :run]
[29:14][Test binary_divide() to see that it doesn't work][:"logic design" :run]
[30:42][Fix binary_divide() to left-shift the denominator by sum_bits - 1 before looping through the bits, right-shift the denominator at the end of each iteration of its loop, and preserve the original denominator for the assertion][:"logic design"]
[34:21][:Run it to find that binary_divide() works][:"logic design"]
[34:41][Optimise binary_divide() as binary_divide2()][:"logic design" :optimisation]
[39:35][:Run it to see that the optimised binary_divide2() works, noting the possibility to put q and r in a single shift register][:"logic design" :optimisation]
[40:27][Shift register][:hardware :speech]
[42:11][Rename the divide functions to sw_*() and introduce our :hardware binary_divider()][:"logic design"]
[49:00][Define Example36 as a divider][:"logic design"]
[50:29][Simulate our divider to see that it did not work][:emulation :"logic design" :run]
[50:42][Fix our divider simulator to pull the quotient out of the result, and trace binary_divider()][:"logic design"]
[52:22][Check out our trace of binary_divider()][:emulation :"logic design" :run]
[53:03][Fix binary_divider() to left-shift r][:"logic design"]
[53:55][Continue to scrutinise our binary_divider() trace to see that r wrapped around][:emulation :"logic design" :run]
[56:42][@vaualbus][How will we handle floating point numbers?][:"numeral system"]
[56:54][Scrutinise our binary_divider() trace now including d2][:emulation :"logic design" :run]
[59:01][Fix binary_divider() to left-shift d2 by len(d) - 1][:"logic design"]
[1:00:19][Trace q and r at both the start and end of the loop in binary_divider()][:"logic design"]
[1:00:35][Check our binary_divider() trace to see "post r" of 240][:emulation :"logic design" :run]
[1:02:03][Print the generated code of Example36's binary_divider()][:"logic design"]
[1:02:39][Check the code of Example36][:"logic design" :research]
[1:04:59][Distinguish unary and binary minus in the compiler][:"code generation"]
[1:07:25][Check the newly generated code of Example36's binary_divider()][:"logic design" :research]
[1:10:06][Remove the test unary minus from binary_divider() and simulate it to see that it works][:emulation :"logic design" :run]
[1:10:39][Slightly rewrite binary_divider()][:"logic design"]
[1:12:08][Reflect of our restoring division, with thoughts on possible optimisations][:"logic design" :optimisation :speech]
[1:14:04][Optimise binary_divider() as binary_divider2()][:"logic design" :optimisation]
[1:18:01][Simulate binary_divider2() to see that it works][:emulation :"logic design" :run]
[1:18:23][Understanding the need to 0-extend the difference of a subtraction in order to derive its sign][:"logic design" :speech]
[1:19:14][Restoring division[ref
site=Wikipedia
page="Division algorithm"
url=https://en.wikipedia.org/wiki/Division_algorithm]][:"logic design" :research]
[1:20:45][Introduce nonrestoring_binary_divider()[ref
site=Wikipedia
page="Division algorithm"
url=https://en.wikipedia.org/wiki/Division_algorithm]][:"logic design"]
[1:27:09][Simulate nonrestoring_binary_divider() and fail the test][:emulation :"logic design" :run]
[1:28:55][Fix nonrestoring_binary_divider() to mux between the correct q, before tracing it][:"logic design"]
[1:30:58][Check out the trace of nonrestoring_binary_divider()][:emulation :"logic design" :run]
[1:32:43][Work through non-restoring division from first principles[ref
site=Wikipedia
page="Division algorithm"
url=https://en.wikipedia.org/wiki/Division_algorithm]][:"logic design" :speech]
[1:35:28][Enable nonrestoring_binary_divider() to fix up q and r if the remainder is negative[ref
site=Wikipedia
page="Division algorithm"
url=https://en.wikipedia.org/wiki/Division_algorithm]][:"logic design"]
[1:44:47][Trace nonrestoring_binary_divider()][:emulation :"logic design" :programming :run]
[1:46:27][Introduce convert_signed() for the tracing code to use][:"debug system"]
[1:51:27][Enable signed in the nonrestoring_binary_divider() tracing][:"logic design"]
[1:51:53][Scrutinise the trace of nonrestoring_binary_divider() to determine that the arithmetic right-shift is misbehaving][:emulation :"logic design" :run]
[1:53:22][Enable nonrestoring_binary_divider() to perform arithmetic right-shift where necessary][:"logic design"]
[1:53:38][Simulate nonrestoring_binary_divider() and still fail the test][:emulation :"logic design" :run]
[1:54:59][Fix nonrestoring_binary_divider() to shift r in the correct direction (i.e. left)][:"logic design"]
[1:56:23][Simulate nonrestoring_binary_divider(), fail the test and consult the trace[ref
site=Wikipedia
page="Division algorithm"
url=https://en.wikipedia.org/wiki/Division_algorithm]][:emulation :"logic design" :run]
[2:02:37][Change nonrestoring_binary_divider() to pre-shift r][:"logic design"]
[2:02:55][Simulate nonrestoring_binary_divider() and still fail the test][:emulation :"logic design" :run]
[2:03:23][Determine to go and think about this some more][:speech]
[2:06:27][Glimpse into the future on sequential circuits][:speech]
[/video]