From 813d57907e2ee56721375ddc95e99eecc099ec11 Mon Sep 17 00:00:00 2001 From: Matt Mascarenhas Date: Thu, 9 Aug 2018 20:18:17 +0100 Subject: [PATCH] Annotate bitwise059 --- pervognsen/bitwise/bitwise/bitwise059.hmml | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 pervognsen/bitwise/bitwise/bitwise059.hmml diff --git a/pervognsen/bitwise/bitwise/bitwise059.hmml b/pervognsen/bitwise/bitwise/bitwise059.hmml new file mode 100644 index 0000000..09ac224 --- /dev/null +++ b/pervognsen/bitwise/bitwise/bitwise059.hmml @@ -0,0 +1,57 @@ +[video member=pervognsen stream_platform=twitch project=bitwise title="Sequential Logic, Part 3" vod_platform=youtube id=wbS9A16itDg annotator=Miblo] +[0:07][Recap and set the stage for the day covering :memory][:speech] +[1:21][@sharlock93][Is the timing different now?] +[1:47][Synthesising :memory out of registers, muxers and decoders][:"sequential logic" :speech] +[2:42][Introduce memory()][:memory :"sequential logic"] +[5:03][Introduce ispow2()][:mathematics] +[5:34][Continue to implement memory()][:memory :"sequential logic"] +[7:16][Introduce a generalised recursive mux()][:"logic design"] +[9:37][Implement a read port in memory(), noting that it is a combinational or asynchronous read port][:memory :"sequential logic"] +[10:42][Fix module() decoration of functions][:"logic design"] +[14:18][Try and instantiate some :memory, fixing a typo in mux()][:"sequential logic"] +[14:44][Inspect our :memory in the debugger][:run :"sequential logic"] +[15:19][Implement a write port in memory()][:memory :"sequential logic"] +[18:10][Decoding an 8-bit binary address to an array of 256 bit signals][:speech] +[20:02][Finish implementing a write port in memory()][:memory :"sequential logic"] +[21:19][Introduce example43_test() as a simple :memory test][:emulation :"sequential logic"] +[24:10][:Run simulate_test() successfully on example43_test][:emulation :memory :"sequential logic"] +[24:14][Augment example43_test() with a scramble() function][:emulation :hashing :memory :"sequential logic"] +[26:56][:Run simulate_test() unsuccessfully on example43_test][:emulation :memory :"sequential logic"] +[27:18][Fix example43_test() to set the write_enable][:emulation :memory :"sequential logic"] +[27:48][:Run simulate_test() successfully on example43_test, and step through it to prove it][:emulation :memory :"sequential logic"] +[28:22][Adding more read / write memory ports, using a one-hot mux][:memory :"sequential logic" :speech] +[31:26][Rename memory() to register_memory() and set up to create a builtin :memory primitive][:"sequential logic"] +[33:50][Introduce a new memory() and Memory class as a builtin primitive][:memory :"sequential logic"] +[38:09][See if someone's at the door][:admin] +[38:19][:afk] +[38:41][Return][:admin] +[38:56][Define MemoryReadPort class][:memory :"sequential logic"] +[44:53][Remove MemoryReadPort in favour of having only one read and write port by default][:memory :"sequential logic"] +[48:53][Create Example43 as a :memory module][:"sequential logic"] +[51:21][:Run it to determine that it at least type-checked][:memory :"sequential logic"] +[52:06][Check the graph of our memory module][:"debug visualisation" :memory :run :"sequential logic"] +[52:29][Try to compile our Example43 memory module][:emulation :memory :"sequential logic"] +[52:41][Simulate Example43 to see that it does explode][:emulation :memory :run :"sequential logic"] +[53:02][Consider how to enable linearize() to handle unconnected output nodes][:"code generation" :"logic design" :speech] +[55:34][Enable linearize() to handle abstract modules that cannot get inlined, defining a dummy GenericMemory class][:"code generation" :"logic design"] +[58:26][:Run it to find that it fails on the :memory module and investigate why][:"sequential logic"] +[1:02:05][Revert our builtin :memory primitive code and use our model memory for the rest of the stream][:"sequential logic"] +[1:04:06][:Run it to see that it seems to work][:emulation :memory :"sequential logic"] +[1:04:16][FIFO (first-in, first-out][:memory :speech] +[1:05:31][Introduce fifo() module][:memory :"sequential logic"] +[1:15:31][Write a test of our fifo module with a producer and consumer][:emulation :memory :"sequential logic"] +[1:21:13][:Run our fifo test, unsuccessfully][:emulation :memory :"sequential logic"] +[1:21:42][Make fifo() set the dequeue_data to output(mem.read_data)][:memory :"sequential logic"] +[1:22:15][Simulate our fifo, fail the test and investigate why][:emulation :memory :run :"sequential logic"] +[1:23:26][Respecify "empty" and "full" in fifo() as their inverse, and make fifo_test_producer() and fifo_test_consumer() yield][:emulation :memory :"sequential logic"] +[1:24:40][Step through our fifo test to determine that dequeue_data is incorrectly set on the second round][:emulation :memory :run :"sequential logic"] +[1:25:53][Try to enable fifo() to keep the queue readiness and reading in phase by delaying the output][:memory :"sequential logic"] +[1:28:15][Simulate our fifo, fail the test again and continue to investigate why][:emulation :memory :run :"sequential logic"] +[1:29:32][Try to enable fifo() to keep everything in phase by also reading from the next address][:memory :"sequential logic"] +[1:31:29][Change our fifo test to enqueue values starting from 1][:emulation :memory :"sequential logic"] +[1:31:54][Simulate our fifo to see that it all worked, but failed the test][:emulation :memory :run :"sequential logic"] +[1:32:11][Change our fifo test assertion to mask the test value, and then switch it all back to enqueuing values starting from 0][:emulation :memory :"sequential logic"] +[1:32:49][Simulate our fifo successfully][:emulation :memory :run :"sequential logic"] +[1:33:03][Understanding how fifo() keeps everything in phase][:memory :research :"sequential logic"] +[1:36:48][Call it a day with some final thoughts on our FIFO :memory and a glimpse into the future][:speech] +[/video]