diff --git a/pervognsen/bitwise/bitwise/bitwise047.hmml b/pervognsen/bitwise/bitwise/bitwise047.hmml
index 39bd6d3..67bf147 100644
--- a/pervognsen/bitwise/bitwise/bitwise047.hmml
+++ b/pervognsen/bitwise/bitwise/bitwise047.hmml
@@ -1,2 +1,51 @@
-[video member=pervognsen stream_platform=twitch project=bitwise title="Domain-Specific Languages In Python, Part 5" vod_platform=youtube id=cyVFbdW2Qjw annotator=]
-[/video]
\ No newline at end of file
+[video member=pervognsen stream_platform=twitch project=bitwise title="Domain-Specific Languages In Python, Part 5" vod_platform=youtube id=cyVFbdW2Qjw annotator=Miblo]
+[0:06][Recap and set the stage for the final stream in this portion of the series][:speech]
+[0:57][Review newly added optional display of types and labelling of nodes to our DotGenerator][:language :research]
+[4:19][Review our new parity() circuit][:language :research]
+[5:46][Introduce parity2() as a naive way to XOR a collection of bits][:language]
+[7:46][:Run it to see our graph for parity2()][:"debug visualisation" :language]
+[9:43][:Run it on the original parity() to see our graph with logarithmic depth][:"debug visualisation" :language]
+[12:52][:Run it on LinearXorScanner8 and explain our graph for this][:"debug visualisation" :language]
+[17:56][Compare the LinearXorScanner8 graph with that for Parity8][:"debug visualisation" :language :run]
+[18:35][:Run it on LogarithmicXorScanner8 and explain our graph for this][:"debug visualisation" :language]
+[19:55][Walk through parity(), scan() and scan2(), with a mention of the Brent-Kung adder[ref
+    site=Wikipedia
+    page="Brent–Kung adder"
+    url=https://en.wikipedia.org/wiki/Brent%E2%80%93Kung_adder]][:language :research]
+[26:38][Highlight the skewed fanout in our LogarithmicXorScanner8][:"debug visualisation" :language :run]
+[28:00][Generate a 32-bit LogarithmicXorScanner8 circuit and check out the skewed fanout in its graph][:"debug visualisation" :language :run]
+[29:39][Consider expanding our vocabulary with when() and case(), and optimising our graph visualisation][:"debug visualisation" :language :speech]
+[32:46][Flattening graph slices by short-circuiting the second level of a slice-of-a-slice][:"debug visualisation" :language :speech]
+[34:58][Enable IndexNode to flatten slices][:"debug visualisation" :language]
+[36:21][:Run it to see that there might be a bug][:"debug visualisation" :language]
+[37:55][Step in to IndexNode and inspect the data][:"debug visualisation" :language :run]
+[39:00][Fix IndexNode to correctly flatten slices][:"debug visualisation" :language]
+[39:38][:Run it to see that it looks better][:"debug visualisation" :language]
+[39:47][Enable SliceNode to flatten slices of slices][:"debug visualisation" :language]
+[40:30][:Run it to see our flattened slices of slices, and consider short-circuiting indexing into concatenations][:"debug visualisation" :language]
+[41:46][Loft out the construction part of IndexNode and SliceNode to make_index() and make_slice() respectively][:"debug visualisation" :language]
+[47:45][:Run it to see the same stuff we had before][:"debug visualisation" :language]
+[47:53][Enable make_index() to short-circuit ConcatNode indexing][:"debug visualisation" :language]
+[50:59][:Run it to see that some of it looks dubious][:"debug visualisation" :language]
+[51:59][Consider our previous graph without short-circuiting of concatenation indexing][:"debug visualisation" :language :run]
+[52:34][Continue to investigate why our concatenation indexing doesn't always get flattened][:"debug visualisation" :language :research]
+[59:12][Enable make_index() to recursively apply flattening to ConcatNodes][:"debug visualisation" :language :run]
+[1:00:19][:Run it to see exactly what we wanted to see][:"debug visualisation" :language]
+[1:01:18][Check out the fanout in a 32-bit LogarithmicXorScanner8 circuit][:"debug visualisation" :language :run]
+[1:04:15][Incorporating registers, in the context of a Counter module][:hardware :memory :speech :timing]
+[1:09:34][Introduce RegisterNode][:"debug visualisation" :language]
+[1:13:36][Introduce Counter module][:language]
+[1:14:28][:Run it to see our Counter circuit][:"debug visualisation" :language]
+[1:15:00][Add a value to the RegisterNode()][:"debug visualisation" :language]
+[1:15:11][:Run it to see our Counter circuit][:"debug visualisation" :language]
+[1:15:51][Define __add__ and __radd__ operands for our Counter module to use][:language :mathematics]
+[1:16:47][:Run it to see our Counter circuit, with a cycle][:"debug visualisation" :language]
+[1:17:07][Add an increment input to our Counter module][:"debug visualisation" :language]
+[1:17:30][:Run it to see the terrible layout of our Counter circuit][:"debug visualisation" :language]
+[1:18:10][Change the inc input in our Counter module to an enable input which controls the count via a (newly introduced) WhenNode][:"debug visualisation" :language]
+[1:25:34][:Run it see our Counter circuit with conditional operation][:"debug visualisation" :language]
+[1:26:55][A few words on flipflop enables][:hardware :speech]
+[1:27:58][Change our Counter module to contain a D-flipflop with builtin enable][:"debug visualisation" :language]
+[1:29:26][:Run it to see this Counter module][:"debug visualisation" :language]
+[1:29:43][That's probably enough, with a glimpse into next week's ordered introduction to :hardware][:speech]
+[/video]