diff --git a/miotatsu/riscy/riscy/riscy018.hmml b/miotatsu/riscy/riscy/riscy018.hmml index d63c6e2..4cfb9ef 100644 --- a/miotatsu/riscy/riscy/riscy018.hmml +++ b/miotatsu/riscy/riscy/riscy018.hmml @@ -1,38 +1,38 @@ -[video member=miotatsu stream_platform=twitch project=riscy title="Andrew Waterman & Yunsup Lee Interview" vod_platform=youtube id=Df-o29DkqWw guest=/y_lee guest=/a_waterman annotator=Miblo] -[0:01][Welcome and introduce Andrew Waterman & Yunsup Lee] +[video member=miotatsu stream_platform=twitch project=riscy title="Andrew Waterman & Yunsup Lee Interview" medium=speech vod_platform=youtube id=Df-o29DkqWw guest=y_lee guest=a_waterman annotator=Miblo] +[0:01][Welcome and introduce [@a_waterman Andrew Waterman] & [@y_lee Yunsup Lee]] [1:07][A highlight reel of life stories before RISC-V] -[1:22][Andrew Waterman: Life before RISC-V] -[2:46][Yunsup Lee: Life before RISC-V] +[1:22][@a_waterman][Life before RISC-V] +[2:46][@y_lee][Life before RISC-V] [4:18][Why decide to create a new ISA?] -[4:33][Andrew: On creating a simple basis for performing research] -[6:23][Yunsup: On removing complexity in order to enable development by small teams] +[4:33][@a_waterman][On creating a simple basis for performing research] +[6:23][@y_lee][On removing complexity in order to enable development by small teams] [7:12][What drew you specifically to RISC?] -[7:34][Yunsup: Necessity] -[8:39][Andrew: On following RISC I and RISC II] +[7:34][@y_lee][Necessity] +[8:39][@a_waterman][On following RISC I and RISC II] [9:16][What appealed to you about having it be open :hardware?] -[9:32][Yunsup: Openness enables understanding and learning] -[10:41][Andrew: On finding encouragement in the competition of ideas in the open source community] -[12:57][Yunsup: On the potential for open hardware enabling schools to teach what the industry actually uses] +[9:32][@y_lee][Openness enables understanding and learning] +[10:41][@a_waterman][On finding encouragement in the competition of ideas in the open source community] +[12:57][@y_lee][On the potential for open hardware enabling schools to teach what the industry actually uses] [13:36][What are you hoping to see happen in the world of RISC-V?] -[13:51][Andrew: A RISC ISA is suitable for many domains of computing, from the lowest to the highest performing computing] -[15:15][Yunsup: On the need for customisation with the end of Moore's Law] +[13:51][@a_waterman][A RISC ISA is suitable for many domains of computing, from the lowest to the highest performing computing] +[15:15][@y_lee][On the need for customisation with the end of Moore's Law] [16:01][Do you think RISC-V being in anything and everything is an attainable goal, and what markets may RISC-V most thrive in?] -[16:24][Andrew: Embedded systems contain all sorts of chips] -[17:21][Yunsup: New markets] +[16:24][@a_waterman][Embedded systems contain all sorts of chips] +[17:21][@y_lee][New markets] [18:23][@hossein1387][My question is, considering the huge investment that is currently happening in custom chips for :AI, how do you think SiFive can attract investors in the field of AI to pay more attention to your platform?] -[18:50][Yunsup: Customisable chips may well serve machine learning :research][:ai] -[20:27][Andrew: Evaluation of neural networks will frequently be done in energy constrained environments] +[18:50][@y_lee][Customisable chips may well serve machine learning :research][:ai] +[20:27][@a_waterman][Evaluation of neural networks will frequently be done in energy constrained environments] [21:11][Can you tell us a bit about SiFive in terms of what they offer customers?] -[21:29][Yunsup: Democratising access to custom silicon][:hardware] -[23:07][Andrew: On the expense of building custom chips using a proprietary ISA] +[21:29][@y_lee][Democratising access to custom silicon][:hardware] +[23:07][@a_waterman][On the expense of building custom chips using a proprietary ISA] [24:46][What are the coolest HiFive1 projects you've seen?] -[25:01][Yunsup: Printer controller and Zephyr port] -[26:30][Andrew: On the community porting the realtime Zephyr operating system to the HiFive1] +[25:01][@y_lee][Printer controller and Zephyr port] +[26:30][@a_waterman][On the community porting the realtime Zephyr operating system to the HiFive1] [27:12][Will SiFive release products using Freedom Unleashed?] -[27:30][Yunsup: Why build the HiFive1 board] -[28:22][Andrew: Excitement for a Unix capable RISC-V system coming out relatively soon] +[27:30][@y_lee][Why build the HiFive1 board] +[28:22][@a_waterman][Excitement for a Unix capable RISC-V system coming out relatively soon] [28:41][Any resources to recommend for learning about RISC-V or open :hardware in general?] -[28:53][Andrew: The RISC-V User-Level ISA Specification[ref +[28:53][@a_waterman][The RISC-V User-Level ISA Specification[ref site=RISC-V page="User-Level ISA Specification v2.1" url=https://riscv.org/specifications] and two text books coming out this year based on Computer Organization and Design[ref @@ -46,28 +46,28 @@ publisher="Morgan Kaufmann" isbn=9780123838728 url=https://www.elsevier.com/books/computer-architecture/hennessy/978-0-12-383872-8]] -[29:55][Yunsup: Graduate-level course at Berkeley] -[31:25][Andrew: Plug Berkeley's use of RISC-V in the classroom] +[29:55][@y_lee][Graduate-level course at Berkeley] +[31:25][@a_waterman][Plug Berkeley's use of RISC-V in the classroom] [32:05][What advice do you have for those looking to get involved in the RISC-V community?] -[32:24][Yunsup: If you want to learn how computers work, RISC-V is a good resource] -[34:27][Andrew: There's a lot of work to be done on compilers, operating systems, software, microarchitecture, etc] +[32:24][@y_lee][If you want to learn how computers work, RISC-V is a good resource] +[34:27][@a_waterman][There's a lot of work to be done on compilers, operating systems, software, microarchitecture, etc] [35:04][@hossein1387][Is there any plan for MOOC (massive online open courses)?] -[35:45][Andrew: On Berkeley possibly teaching CS61C as an online course[ref +[35:45][@a_waterman][On Berkeley possibly teaching CS61C as an online course[ref site="University of California, Berkeley" page="Great Ideas in Computer Architecture (Machine Structures)" url=http://inst.eecs.berkeley.edu/~cs61c/sp17/]] [35:57][Point out the SiFive Forums as a good resource[ref site="SiFive Forums" url=https://forums.sifive.com/]] -[36:12][Andrew: Shout-out to Megan Wachs] +[36:12][@a_waterman][Shout-out to Megan Wachs] [36:35][Give it a minute to see if some questions pop up] [37:38][Suppose that is everything, but wait...] [37:59][@hossein1387][What is your answer to Linus Torvalds when he said ISA is not important and it's the community around ISA that matters?] -[38:15][Andrew: On ISAs not mattering, especially in high end computing] -[39:28][Yunsup: Why not RISC-V if instruction sets don't matter?] -[39:50][Andrew: It takes a village, so if you have resources to help port to RISC-V, pitch in!] -[40:03][@miblo][I missed the start, but I was wondering: Do you personally have anything you'd like to see RISC-V users do that isn't necessarily endorsed or endorsable by SiFive?] -[40:28][Andrew: The more implementations there are, the better the project will be for everyone] -[41:43][Yunsup: It gets stronger the more people look at it] +[38:15][@a_waterman][On ISAs not mattering, especially in high end computing] +[39:28][@y_lee][Why not RISC-V if instruction sets don't matter?] +[39:50][@a_waterman][It takes a village, so if you have resources to help port to RISC-V, pitch in!] +[40:03][@Miblo][I missed the start, but I was wondering: Do you personally have anything you'd like to see RISC-V users do that isn't necessarily endorsed or endorsable by SiFive?] +[40:28][@a_waterman][The more implementations there are, the better the project will be for everyone] +[41:43][@y_lee][It gets stronger the more people look at it] [42:57][That's the end for real] [/video]