From c79cc5b05e0dc6ff3256dd78cfc877a5b5c8a639 Mon Sep 17 00:00:00 2001 From: Matt Mascarenhas Date: Tue, 26 Jun 2018 22:55:14 +0100 Subject: [PATCH] Annotate bitwise042 --- pervognsen/bitwise/bitwise/bitwise042.hmml | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 pervognsen/bitwise/bitwise/bitwise042.hmml diff --git a/pervognsen/bitwise/bitwise/bitwise042.hmml b/pervognsen/bitwise/bitwise/bitwise042.hmml new file mode 100644 index 0000000..6236258 --- /dev/null +++ b/pervognsen/bitwise/bitwise/bitwise042.hmml @@ -0,0 +1,42 @@ +[video member=pervognsen stream_platform=twitch project=bitwise medium=speech title="How To Program Assembly, Part 3" vod_platform=youtube id=7ye-sMA15Qs annotator=Miblo] +[0:00][Recap and set the stage for the final part of the assembly writing tutorial][:asm] +[0:30][Shout-out to godbolt[ref + site="Compiler Explorer" + url=https://godbolt.org/] for its assembly exploration capabilities][:asm :research] +[4:25][Switch statements][:asm :language] +[8:15][Implementing switch using a jump table][:language] +[15:10][Throw a switch statement into godbolt[ref + site="Compiler Explorer" + url=https://godbolt.org/] to see what riscv32 clang and x86-64 MSVC generate][:asm :research] +[21:36][Compressing a lookup table when it has few distinct entries relative to the total number of keys][:compression :memory] +[24:28][Lowering a jump table-based switch statement, without the compressed table indirection, from C to assembly][:asm :language] +[38:14][Functions[ref + author="Andrew Waterman and Krste Asanović" + title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA" + url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:asm :language] +[51:55][Calls and returns, and RISC-V's JAL and JMP instructions][:asm :isa :language] +[58:35][Lowering our example fact() function from C to assembly[ref + author="Andrew Waterman and Krste Asanović" + title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA" + url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:asm :language] +[1:07:00][@cubercaleb][What is meant by the function epilogue and prologue? Is that just a fancy way of saying "stack setup and tear-down", or does something actually happen?[ref + site=Wikipedia + page="Function prologue" + url=https://en.wikipedia.org/wiki/Function_prologue]] +[1:07:59][Lowering fact() from C to assembly using a callee-save register][:asm :language] +[1:13:18][Designating registers as caller- vs callee-save, as demonstrated by leaf functions][:asm :language] +[1:17:33][Summarise the handling of more complex functions][:asm :language] +[1:18:30][@cubercaleb][Isn't ret a CISC-like instruction, e.g. MIPS requires `jr $ra`?[ref + author="Andrew Waterman and Krste Asanović" + title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA" + url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa] +[1:20:53][Consider going on to nested / compound expressions][:asm :language] +[1:21:43][Note the assumption that local variables don't need to be spilt][:asm :language :memory] +[1:25:08][Flattening expressions and register allocations][:asm :language :memory] +[1:29:30][Flattening a right-associative expression[ref + site=Wikipedia + page="Sethi–Ullman algorithm" + url=https://en.wikipedia.org/wiki/Sethi%E2%80%93Ullman_algorithm]][:asm :language :memory] +[1:36:02][Summarise the expression and register allocations information][:asm :language :memory] +[1:37:18][That's it for today] +[/video]