[video member=pervognsen stream_platform=twitch project=bitwise medium=speech title="Packages Demo & RISC-V Intro" vod_platform=youtube id=dvaTa6UHR48 annotator=Miblo]
[0:09][Recap and set the stage for the day]
[3:39][Packages: 3 Parts][:"file io"]
[6:36][Demo packages, as used in test1.ion][:"file io"]
[10:47][Explain the idempotent nature of packages, and the ability to import the same file (e.g. libc) multiple times][:"file io" :research]
[12:04][Bulk imports][:"file io"]
[15:09][:Run ion to demo use of the IONHOME environment variable][:"file io"]
[19:06][Explain the change to noir to denote foreign C files][:"file io"]
[20:30][Tree shaking[ref
    site=Wikipedia
    page="Tree shaking"
    url=https://en.wikipedia.org/wiki/Tree_shaking] and its influence on package processing][:"code generation" :"file io" :research]
[28:22][Demo lazy :"code generation" by introducing an invalid bogus_func()]
[34:09][Review the package :parsing code, including the notion of the current_package][:"file io" :research]
[38:48][Explain the idempotency of sym_global_put(), and optional names for symbols][:"error handling" :"file io" :research]
[45:49][Note that resolve_package_syms() only resolves symbols from the home package, unless you import using an explicit name][:"file io" :research]
[47:42][Review changes to the generator to handle packages, including get_gen_name_or_default()][:"code generation" :"file io" :research]
[52:15][Emphasise that this all works on gcc and msys2 on Windows, and gcc on Linux, and has been reported as working on Macintosh]
[53:17][Q&A][:speech]
[53:56][@printf_armin][So it searches in IONPATH for the file, but what happens when there are two files with equal names in the path?][:"file io"]
[55:12][Set up to transition to RISC-V]
[56:44][Introduce RISC-V[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf] with mentions of 'The Case for the Reduced Instruction Set Computer'[ref
        author="David A. Patterson and David R. Ditzel"
        title="The Case for the Reduced Instruction Set Computer"
        url=https://www.cs.utexas.edu/users/fussell/courses/cs352h/papers/risc.pdf] and John Cocke[ref
            site=Wikipedia
            page="John Cocke"
            url=https://en.wikipedia.org/wiki/John_Cocke]][:isa]
[1:01:01][Note that RISC-V is a tiered architecture[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[1:07:31][Recommend reading Chapter 2.2 Base Instruction Formats[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[1:11:03][Consider the major distinguishing feature of RISC-V to be its focus on load-store architecture[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf] as opposed to x86][:isa]
[1:18:30][Plan for the coming weeks of working with RISC-V and beyond, with reasons why we'll be emulating rather than working on real hardware][:emulation :isa]
[1:26:46][Q&A]
[1:27:16][@xanatos387][Will RISC-V in FPGA be limited to 32-bit due to gate count limitations, or is it plausible to do 64-bit?][:hardware :memory]
[1:30:10][@sci4me][Assembler first probably?]
[1:30:29][Sketch out the style of emulator we expect to build][:"code generation" :emulation]
[1:37:42][@xanatos387][@pervognsen: I understand the compile-to-C backend is never going away, but just hypothetically, if that wasn't a constraint, what would you change / add about Ion while still staying in the same general design space?][:language]
[1:40:33][Wrap it up with a reminder to read Chapter 2.2 Base Instruction Formats[ref
    author="Andrew Waterman and Krste Asanović"
    title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
    url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
[/video]