58 lines
4.5 KiB
Plaintext
58 lines
4.5 KiB
Plaintext
[video member=pervognsen stream_platform=twitch project=bitwise title="RISC-V Toolchain Implementation" vod_platform=youtube id=zDOd3inaOsY annotator=Miblo]
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[0:09][Recap and set the stage for the day, with a note that off-stream work will now be covered in write-ups, rather than on stream][:speech]
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[2:05][Plan to create two tools: assembler and simulator][:isa :speech]
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[5:44][Chapter 19 - RV32/64G Instruction Set Listings[ref
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author="Andrew Waterman and Krste Asanović"
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title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
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url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa :research]
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[8:05][Dive into writing our RISC-V assembler, starting with an Instruction struct[ref
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author="Andrew Waterman and Krste Asanović"
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title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
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url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
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[13:30][Introduce decode_instruction() and encode_instruction() and declare our immediate field masks[ref
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author="Andrew Waterman and Krste Asanović"
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title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
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url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
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[20:47][Add cases for LUI, AUIPC, JAL, JALR and the branch instructions in decode_instruction()[ref
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author="Andrew Waterman and Krste Asanović"
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title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
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url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
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[35:45][Introduce empty decode_u_instruction(), decode_j_instruction(), decode_b_instruction() and decode_i_instruction()][:isa]
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[36:21][Look into handling the "'riscv_Op': undeclared identifier" error]
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[38:54][Just disable typeinfo for now][:admin]
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[39:36][Add cases for the load and store instructions in decode_instruction(), also introducing an empty decode_s_instruction()[ref
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author="Andrew Waterman and Krste Asanović"
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title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
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url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
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[44:27][Add a case for the integer register-immediate instructions in decode_instruction()[ref
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author="Andrew Waterman and Krste Asanović"
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title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
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url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
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[58:57][Add a case for the FENCE / FENCE.I instructions in decode_instruction()[ref
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author="Andrew Waterman and Krste Asanović"
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title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
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url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
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[1:00:38][Enable Ion's scan_int() to skip _ delimiters in int declarations][:parsing]
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[1:03:26][Finish up the FENCE / FENCE.I case in decode_instruction()[ref
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author="Andrew Waterman and Krste Asanović"
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title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
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url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
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[1:09:00][Add a case for the integer register-register instructions in decode_instruction()[ref
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author="Andrew Waterman and Krste Asanović"
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title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
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url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
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[1:18:27][Add a case for the environment call and breakpoints instructions ECALL and EBREAK in decode_instruction()[ref
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author="Andrew Waterman and Krste Asanović"
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title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
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url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
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[1:22:25][Include the CSR (Control and Status Register) instructions in the ECALL / EBREAK case in decode_instruction(), introducing decode_csr_instruction()[ref
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author="Andrew Waterman and Krste Asanović"
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title="The RISC-V Instruction Set Manual - Volume 1: User-Level ISA"
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url=https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf]][:isa]
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[1:25:35][Reflect on the day's work][:speech]
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[1:26:55][Q&A][:speech]
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[1:28:03][@arbitraryslayer][Hi @pervognsen, I have a quick question. Why do you think C is preferred over C++ for system level when C++ has more features than C?][:language]
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[1:29:11][@nothings2][Also I wonder if bitfields would make instruction decoding cleaner][:language]
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[1:29:51][Cut over to the extra stream][:speech]
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[/video]
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