cinera_handmade.network/miotatsu/riscy/riscy/riscy051.hmml

[video member=miotatsu stream_platform=twitch project=riscy title="Studying entry.S" vod_platform=youtube id=vBlJBDlP6gY annotator=Miblo]
[0:07][Recap and set the stage for the day, with a plug of the RISCY BUSINESS GitHub[ref
    site=GitHub
    page="RISCY BUSINESS"
    url=https://github.com/riscy-business]]
[6:08][Embark on studying entry.S, our first substantial look at GNU assembly][:asm :research]
[11:05][Adding to the stack pointer]
[14:39][mcause and mepc to the csrr]
[17:11][Describe stack and heap :memory, including brk[ref
    site="Linux man page"
    page=brk
    url=https://linux.die.net/man/2/brk]][:research]
[22:15][Hunt the documentation for the register names[ref
    site=RISC-V
    page="User-Level ISA Specification v2.1"
    url=https://riscv.org/specifications]][:research]
[27:18][Plug SiFive's launch announcement of the U54-MC Coreplex[ref
    site=SiFive
    page="SiFive Launches First RISC-V Based CPU Core with Linux Support"
    url=https://www.sifive.com/posts/2017/10/04/sifive-launches-first-risc-v-based-cpu-core-with-linux-support/] and Raptor Computing Systems[ref
    site="Raptor Computing Systems"
    url=https://www.raptorcs.com/] with dreams for a RISC-V desktop][:research]
[36:28][Continue the description of stack and heap :memory allocation]
[39:04][Plug nwr_mem.h, a user-space :memory allocator[ref
    site="RISCY BUSINESS Forums"
    page="nwr_mem.h"
    url=https://riscy.handmade.network/forums/t/2471-nwr_mem.h]][:research]
[42:30][Argument registers: a0, a1 and a2[ref
    site=GitHub
    page="RISC-V ELF psABI specification"
    url=https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md]][:research]
[47:12][Hunt the documentation for the control status register[ref
    site="RISC-V"
    page="Draft Privileged ISA Specification v1.9.1"
    url=https://riscv.org/specifications/privileged-isa/]][:research]
[49:46][Read about the Machine Exception Program Counter (mepc) and Machine Cause Register (mcause)[ref
    site="RISC-V"
    page="Draft Privileged ISA Specification v1.9.1"
    url=https://riscv.org/specifications/privileged-isa/]][:research]
[56:52][Refresh our memories about the CSR Instructions[ref
    site=RISC-V
    page="User-Level ISA Specification v2.1"
    url=https://riscv.org/specifications]][:research]
[58:58][Reading the exception data and stack pointer into argument registers[ref
    site=GitHub
    page="RISC-V ELF psABI specification"
    url=https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md]][:research]
[1:02:19][Calling handle_trap and writing the return value into mepc[ref
    site=RISC-V
    page="User-Level ISA Specification v2.1"
    url=https://riscv.org/specifications]][:research]
[1:05:17][Read about the Machine Exception Program Counter (mepc)[ref
    site="RISC-V"
    page="Draft Privileged ISA Specification v1.9.1"
    url=https://riscv.org/specifications/privileged-isa/]][:research]
[1:06:28][Study handle_trap() in init.c, wondering why write the stack pointer into a2][:research]
[1:09:54][Draft questions in the Big RISCY BUSINESS Question Thread as to why entry.S writes the stack pointer into the trap handler, and the trap handler's return value into mepc[ref
    site="SiFive Forums"
    page="The Big RISCY BUSINESS Question Thread"
    url=https://forums.sifive.com/t/the-big-riscy-business-question-thread/531/4]][:research]
[1:14:54][Continue reading entry.S, using li (load immediate) to load MSTATUS_MPP into a temporary register, and then storing that in mstatus][:research]
[1:21:48][Read about the Machine Status Register (mstatus)[ref
    site="RISC-V"
    page="Draft Privileged ISA Specification v1.9.1"
    url=https://riscv.org/specifications/privileged-isa/] and CSRS[ref
    site=RISC-V
    page="User-Level ISA Specification v2.1"
    url=https://riscv.org/specifications]]
[1:25:22][Consult encoding.h for the definition of MSTATUS_MPP, and locate this in the mstatus register[ref
    site="RISC-V"
    page="Draft Privileged ISA Specification v1.9.1"
    url=https://riscv.org/specifications/privileged-isa/]][:research]
[1:30:04][Read about Memory Privilege in mstatus Register[ref
    site="RISC-V"
    page="Draft Privileged ISA Specification v1.9.1"
    url=https://riscv.org/specifications/privileged-isa/]][:research]
[1:32:37][Plug the SiFive webinar[ref
    site="SiFive"
    page="Getting started with SiFive IP"
    url=https://info.sifive.com/risc-v-webinar]][:research]
[1:37:02][Read about MPP and MRET[ref
    site="RISC-V"
    page="Draft Privileged ISA Specification v1.9.1"
    url=https://riscv.org/specifications/privileged-isa/]][:research]
[1:44:19][Wonder if we swap MPP with the privileged mode (thus switching to user-mode), or just store the privileged mode into MPP]
[1:45:30][Continue studying entry.S: staying in machine-mode, and then restoring our registers and deallocate]
[1:50:59][Read about the Machine-Mode Trap-Return Instruction (MRET)[ref
    site="RISC-V"
    page="Draft Privileged ISA Specification v1.9.1"
    url=https://riscv.org/specifications/privileged-isa/]][:research]
[1:55:13][Determine to learn the GNU assembler syntax[ref
    site="GNU Binutils"
    page="Using as"
    url=https://sourceware.org/binutils/docs-2.28/as/index.html]][:research]
[2:00:28][Wrap it up with thoughts about sleep and streaming schedules]
[2:03:52][Shout-out to @DannyFritz for the support]
[/video]