34 lines
2.3 KiB
Plaintext
34 lines
2.3 KiB
Plaintext
[video member=miotatsu stream_platform=twitch project=riscy title="Getting Back to the Code" vod_platform=youtube id=ozKRGzd6Q4E annotator=Miblo]
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[0:08][Recap and set the stage for the day]
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[0:57][Sign extension in two's complement[ref
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site=Wikipedia
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page="Sign extension"
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url=https://en.wikipedia.org/wiki/Sign_extension]][:blackboard :research]
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[7:45][@hossein1387][You can do a two's complement on 1000_0000 to get the positive value]
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[10:07][:Research setting only the most significant bit in two's complement[ref
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site=Wikipedia
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page="Two's complement"
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url=https://en.wikipedia.org/wiki/Two's_complement]]
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[15:19][Refresh our memory on the Base Instruction Formats and the Immediates with regard to sign extension[ref
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site=RISC-V"
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page="User-Level ISA Specification v2.1"
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url=https://riscv.org/specifications]][:research]
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[19:25][Read about the Integer Register-Immediate Instructions][:research]
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[22:54][Adding unsigned immediates][:blackboard]
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[23:25][@hossein1387][For the adder it does not matter if it's a sign or signed]
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[26:48][Adding unsigned 42 to 128 using sign extension (with incorrect results)][:blackboard]
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[31:47][@hossein1387][But I remember in Computer Architecture class, for ALU, depending on the instruction being signed or unsigned, we had to do a two's complement before passing the number to the, let's say, adder]
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[34:27][@hossein1387][I have a list of instructions for RISC-V and I can only see ADD and ADDI]
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[35:28][Consider unsigned immediate adding to be a gotcha if coding in assembly][:asm :blackboard :research]
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[38:08][@hossein1387][Sorry, I found two more. This what I found: ADDI ADD ADDIW ADDW]
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[40:27][@hossein1387][By the way I am reading the RTL for instructions]
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[41:25][@hossein1387][[ref
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site=GitHub
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page=instructions.scala
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url=https://github.com/ucb-bar/rocket/blob/master/src/main/scala/instructions.scala]]
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[44:53][Read about the Control and Status Register Instructions with a view to understanding the < 32 test in clear_csr()][:research]
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[50:29][Read about the rs1 and rd, and RISC-V user-level base integer register state][:research]
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[54:48][Read about the types of immediate produced by RISC-V instructions][:research]
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[1:01:09][Determine to ask in the SiFive Forums about the < 32 test in clear_csr()]
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[/video]
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