53 lines
2.8 KiB
Plaintext
53 lines
2.8 KiB
Plaintext
[video member=miotatsu stream_platform=twitch project=riscy title="BareD, Story Time, & measure_cpu_freq" vod_platform=youtube id=A3WD0IVXD64 annotator=Miblo]
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[0:08][Recap and set the stage for the day]
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[0:57][Consult forum responses regarding zero-initialisation[ref
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site="SiFive Forums"
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page="The Big RISCY BUSINESS Question Thread"
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url=https://forums.sifive.com/t/the-big-riscy-business-question-thread/531/4]][:platform :research]
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[3:14][Mention an upcoming collaboration with @RiskyFive]
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[6:07][Walk through BareD[ref
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site=GitHub
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page=BareD
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url=https://github.com/miotatsu/BareD]][:language]
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[10:02][BareD's cstr.d[ref
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site=GitHub
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page=BareD
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url=https://github.com/miotatsu/BareD]][:language :"string manipulation"]
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[13:06][BareD's platform.d[ref
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site=GitHub
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page=BareD
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url=https://github.com/miotatsu/BareD]][:language :memory :"platform layer"]
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[18:47][BareD's ldc_linux_x86_64.d[ref
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site=GitHub
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page=BareD
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url=https://github.com/miotatsu/BareD]][:language :"platform layer"]
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[26:20][Plug "Writing C software without the standard library: Linux Edition"[ref
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site="Franc\[e\]sco's Gopherspace"
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page="Writing C software without the standard library: Linux Edition"
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url=http://weeb.ddns.net/0/programming/c_without_standard_library_linux.txt]][:platform :research]
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[27:47][Recount :experience programming Piworld[ref
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site=imgur
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page=Piworld
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url=https://imgur.com/a/vhR3T] in TI_BASIC assembly][:asm]
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[32:29][The origin story of ~riscy][:trivia]
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[34:03][Read through get_cpu_freq() in init.c and study measure_cpu_freq()][:hardware :research]
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[39:20][Marry up the value returned by get_timer_freq() with the documentation on RTC Count Registers[ref
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site="SiFive Developers"
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page="Platform Reference Manual"
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url=https://www.sifive.com/documentation/freedom-soc/freedom-e300-platform-reference-manual/]][:hardware :research]
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[42:28][Marry up mtime_lo() and mtime_hi() with the CLINT documentation[ref
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site="SiFive Developers"
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page="E3 Coreplex Manual"
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url=https://static.dev.sifive.com/pdfjs/web/viewer.html?file=https://static.dev.sifive.com/SiFive-E3-Coreplex-v1.2.pdf]][:hardware :research]
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[47:40][Skim through the Control and Status Registers documentation[ref
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site="RISC-V"
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page="Draft Privileged ISA Specification v1.9.1"
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url=https://riscv.org/specifications/privileged-isa/]][:hardware :research]
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[52:20][Read 3.1.15 Hardware Performance Monitor, on mcycle[ref
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site="RISC-V"
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page="Draft Privileged ISA Specification v1.9.1"
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url=https://riscv.org/specifications/privileged-isa/]][:hardware :research]
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[56:27][Summarise what the mcycle is, and relate it to measure_cpu_freq()][:hardware :research :timing]
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[59:07][Don the Thinking Cap with the determination to work through the CPU frequency formula on the whiteboard]
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[/video]
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