79 lines
6.9 KiB
Plaintext
79 lines
6.9 KiB
Plaintext
[video member=pervognsen stream_platform=twitch project=bitwise title="Logic Design, Part 2" vod_platform=youtube id=HGZzNAxf3sg annotator=Miblo]
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[0:07][Set the stage for the day continuing on :"logic design"][:speech]
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[0:25][Review the notion of boolean logic expressions, and turning a truth table into a sum of products representation][:"logic design" :research]
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[2:06][Review our ability to tabulate functions to their truth table][:"logic design" :research]
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[3:23][Demo function_to_sum_of_products() on an OR function][:"logic design"]
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[4:00][:Run it to see our non-minimal representation of OR, noting that the problem of producing the minimal representation in the general case is NP-complete[ref
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site=Wikipedia
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page="Karnaugh map"
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url=https://en.wikipedia.org/wiki/Karnaugh_map][ref
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site=Wikipedia
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page="Quine–McCluskey algorithm"
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url=https://en.wikipedia.org/wiki/Quine%E2%80%93McCluskey_algorithm][ref
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site=Wikipedia
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page="Espresso heuristic logic minimizer"
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url=https://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer]][:"debug visualisation" :"logic design" :optimisation]
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[7:10][Review off-stream change to using a bit vector for the input][:"logic design" :research]
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[7:46][Review muxes and Shannon expansion][:"logic design" :research]
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[8:35][Consult the graph for our Example3 parity function, highlighting the shareable nodes and bit vector notation, and noting the usefulness of binary decision diagrams][:"debug visualisation" :"logic design" :run]
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[12:33][Note the efficiency of muxes for XOR implementations][:"debug visualisation" :"logic design" :run]
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[13:04][Understanding XOR as a conditional inverter][:"logic design" :speech]
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[14:45][Define Example4 as a 5-bit XOR reduction circuit][:"logic design"]
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[15:33][Check out our 5-bit XOR reduced graph, noting its linear depth][:"debug visualisation" :"logic design" :run]
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[16:03][Introduce reduce() to illustrate linear reduction][:"logic design"]
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[18:13][:Run it to see that the graph is the same as before][:"debug visualisation" :"logic design" :run]
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[18:42][Rename reduce() to linear_reduce() and introduce logarithmic_reduce() as a divide and conquer reduction][:"logic design"]
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[22:16][:Run it to see that it works but is slightly unbalanced for a non-power of two][:"debug visualisation" :"logic design"]
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[22:36][:Run it on an 8-bit input, to see that our graph is fully balanced][:"debug visualisation" :"logic design"]
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[25:21][A few words on divide and conquer and the fork–join model[ref
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site=Wikipedia
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page="Fork–join model"
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url=https://en.wikipedia.org/wiki/Fork%E2%80%93join_model]][:optimisation :speech]
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[26:13][Determine to cover standard circuit elements and write a simulator][:"logic design" :emulation :speech]
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[27:07][Define Example5 as an 8-bit comparison function, applying reduction][:"logic design"]
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[30:38][Check out the graph of our 8-bit comparison function][:"debug visualisation" :"logic design" :run]
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[32:19][Q&A][:speech]
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[32:38][@rygorous][Good thing CPUs don't have silly shit like, say, a "parity" flag bit that is set to match the parity of the last 64-bit result you computed][:"logic design"]
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[33:06][Define Example6 as an 8-bit comparison function in which one of the values is constant][:"logic design"]
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[34:38][Check out our graphed comparison against a constant][:"debug visualisation" :"logic design" :run]
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[35:23][Introduce equals_constant() as a bespoke constant comparer][:"logic design" :optimisation]
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[37:51][Check out our more optimal constant comparison graph][:"debug visualisation" :"logic design" :optimisation :run]
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[39:23][Ripple-carry adder][:"logic design" :speech]
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[43:33][Sketch out add3()][:"logic design" :speech]
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[46:17][Introduce add() as bit-vector adder using our sketched out add3()][:"logic design"]
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[48:15][Define Example7 as a 4-bit ripple-carry adder][:"logic design"]
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[49:21][:Run it to see that the graph is already too much][:"debug visualisation" :"logic design"]
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[49:29][Change Example7 from a 4- to 2-bit ripple-carry adder][:"logic design"]
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[49:56][:Run it to see our 2-bit ripple-carry adder][:"debug visualisation" :"logic design"]
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[50:56][Create Add3 module][:"logic design"]
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[52:47][Check out our 2-bit ripple-carry adder to see more clearly the chain structure of the Add3 modules][:"debug visualisation" :"logic design" :run]
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[53:12][Check out our 4-bit ripple-carry adder, noting that we likely wouldn't make an adder manually for our FPGA, letting our logic synthesis tools pick which adder to instantiate][:"debug visualisation" :"logic design" :run]
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[54:43][@barely_polar][Does this add work with negatives?][:"logic design"]
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[54:49][@rygorous][In two's complement, yes][:"logic design"]
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[56:11][Prevent add() from taking the carry][:"logic design"]
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[56:52][Check out our ripple-carry adder with only internal carries][:"debug visualisation" :"logic design" :optimisation :run]
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[57:15][Consider simplifications to Add3 when the carry is 0, to make a half-adder][:"logic design" :optimisation :speech]
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[1:01:12][Split out the intermediate propagating and generated carry bits in Add3][:"logic design"]
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[1:02:38][Check out the graph of our Add3 half-adder module][:"debug visualisation" :"logic design" :run]
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[1:04:25][Subtraction in two's complement][:"logic design" :speech]
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[1:06:31][Introduce sub() using add(), also having changed add() back to take a carry][:"logic design"]
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[1:07:30][Check out our subtraction graph][:"debug visualisation" :"logic design" :run]
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[1:07:44][Define Example9 as a simple ALU that does addition or subtraction depending on the state of an operation bit][:"logic design"]
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[1:10:17][Check out our addition / subtraction ALU][:"debug visualisation" :"logic design" :run]
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[1:11:48][@barely_polar][Can you talk about the intuition for why flipping the bits and adding 1 is equivalent to subtraction? I can see it's true but don't understand why][:"logic design"]
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[1:14:21][Equality comparison][:"logic design" :speech]
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[1:15:18][Lexicographical equality comparison][:"logic design" :speech]
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[1:18:25][Subtraction and < 0 equality comparison in an ALU][:"logic design" :speech]
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[1:19:53][Change add() to output the carry][:"logic design"]
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[1:21:06][Create Example10 module as a subtraction and < 0 comparator][:"logic design"]
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[1:21:58][Check out our comparison graph][:"debug visualisation" :"logic design" :run]
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[1:22:46][Explicit zero-extension in lieu of the output carry][:"logic design" :speech]
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[1:24:59][Check our workings with [@rygorous Fabian]][:"logic design" :speech]
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[1:25:30][@rygorous][@pervognsen Not actually sure][:"logic design"]
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[1:26:17][Create Example11 module as a signed comparator][:"logic design"]
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[1:26:41][Check out our signed comparator graph][:"debug visualisation" :"logic design" :run]
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[1:26:47][@rygorous][@pervognsen I just know the normal form which uses N and V bits][:"logic design"]
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[1:28:01][Reflect on our comparator modules, noting that you cannot overflow when extending by one bit][:"logic design" :speech]
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[1:31:00][That's a good stopping point][:speech]
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[/video]
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